From 19a5b68db7d73542833d94ec8b23cad6daf0a787 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Wed, 4 Sep 2013 13:22:57 -0400 Subject: arch: Resurrect the NOISA build target and rename it NULL This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc --- src/dev/SConscript | 2 +- src/dev/sinic.cc | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src/dev') diff --git a/src/dev/SConscript b/src/dev/SConscript index cba821f87..1bcddb6ee 100644 --- a/src/dev/SConscript +++ b/src/dev/SConscript @@ -31,7 +31,7 @@ Import('*') -if env['TARGET_ISA'] == 'no': +if env['TARGET_ISA'] == 'null': Return() SimObject('BadDevice.py') diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 02eb8a113..7da70c482 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -32,7 +32,9 @@ #include #include +#ifdef SINIC_VTOPHYS #include "arch/vtophys.hh" +#endif #include "base/compiler.hh" #include "base/debug.hh" #include "base/inet.hh" -- cgit v1.2.3