From 1c0ae90027f0aea96389d0b82f2c732df72fc06c Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 3 Sep 2014 07:43:05 -0400
Subject: arm: Support >2GB of memory for AArch64 systems

---
 src/dev/arm/RealView.py | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'src/dev')

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index ee5993a88..672b17c87 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -184,8 +184,7 @@ class RealView(Platform):
     pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space")
     pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access"
             " be compatible with the pci-generic-host or the legacy host bridge?")
-    mem_start_addr = Param.Addr(0, "Start address of main memory")
-    max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
+    _mem_regions = [(Addr(0), Addr('256MB'))]
 
     def attachPciDevices(self):
         pass
@@ -444,8 +443,7 @@ class RealViewEB(RealView):
         self.smcreg_fake.clk_domain   = clkdomain
 
 class VExpress_EMM(RealView):
-    mem_start_addr = '2GB'
-    max_mem_size = '2GB'
+    _mem_regions = [(Addr('2GB'), Addr('2GB'))]
     pci_cfg_base = 0x30000000
     uart = Pl011(pio_addr=0x1c090000, int_num=37)
     realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
@@ -602,6 +600,9 @@ class VExpress_EMM(RealView):
 class VExpress_EMM64(VExpress_EMM):
     pci_io_base = 0x2f000000
     pci_cfg_gen_offsets = True
+    # Three memory regions are specified totalling 512GB
+    _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
+                    (Addr('512GB'), Addr('480GB'))]
     def setupBootLoader(self, mem_bus, cur_sys, loc):
         self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
         self.nvmem.port = mem_bus.master
-- 
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