From 53e777d6838ac3ca80e6557626f9e99fd93dd0f7 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Fri, 7 Aug 2015 09:59:13 +0100 Subject: base: Declare a type for context IDs Context IDs used to be declared as ad hoc (usually as int). This changeset introduces a typedef for ContextIDs and a constant for invalid context IDs. --- src/dev/arm/gic_pl390.cc | 10 +++++----- src/dev/arm/gic_pl390.hh | 2 +- src/dev/arm/timer_cpulocal.cc | 4 ++-- src/dev/arm/vgic.cc | 10 +++++----- src/dev/arm/vgic.hh | 2 +- src/dev/sinic.cc | 12 ++++++------ src/dev/sinic.hh | 8 ++++---- src/dev/sparc/iob.cc | 4 ++-- 8 files changed, 26 insertions(+), 26 deletions(-) (limited to 'src/dev') diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc index 5a21f6cec..fb1711c92 100644 --- a/src/dev/arm/gic_pl390.cc +++ b/src/dev/arm/gic_pl390.cc @@ -135,7 +135,7 @@ Pl390::readDistributor(PacketPtr pkt) { Addr daddr = pkt->getAddr() - distAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(GIC, "gic distributor read register %#x\n", daddr); @@ -269,7 +269,7 @@ Pl390::readCpu(PacketPtr pkt) Addr daddr = pkt->getAddr() - cpuAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < sys->numRunningContexts()); DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr, @@ -356,7 +356,7 @@ Pl390::writeDistributor(PacketPtr pkt) Addr daddr = pkt->getAddr() - distAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); uint32_t pkt_data M5_VAR_USED; switch (pkt->getSize()) @@ -496,7 +496,7 @@ Pl390::writeCpu(PacketPtr pkt) Addr daddr = pkt->getAddr() - cpuAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); IAR iar; DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n", @@ -546,7 +546,7 @@ Pl390::writeCpu(PacketPtr pkt) } void -Pl390::softInt(int ctx_id, SWI swi) +Pl390::softInt(ContextID ctx_id, SWI swi) { switch (swi.list_type) { case 1: diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh index 1adad6c9a..17946145f 100644 --- a/src/dev/arm/gic_pl390.hh +++ b/src/dev/arm/gic_pl390.hh @@ -210,7 +210,7 @@ class Pl390 : public BaseGic /** software generated interrupt * @param data data to decode that indicates which cpus to interrupt */ - void softInt(int ctx_id, SWI swi); + void softInt(ContextID ctx_id, SWI swi); /** See if some processor interrupt flags need to be enabled/disabled * @param hint which set of interrupts needs to be checked diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc index ac02d099f..11ae3b3d2 100644 --- a/src/dev/arm/timer_cpulocal.cc +++ b/src/dev/arm/timer_cpulocal.cc @@ -75,7 +75,7 @@ CpuLocalTimer::read(PacketPtr pkt) assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); assert(pkt->getSize() == 4); Addr daddr = pkt->getAddr() - pioAddr; - int cpu_id = pkt->req->contextId(); + ContextID cpu_id = pkt->req->contextId(); DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr); assert(cpu_id >= 0); assert(cpu_id < CPU_MAX); @@ -153,7 +153,7 @@ CpuLocalTimer::write(PacketPtr pkt) assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); assert(pkt->getSize() == 4); Addr daddr = pkt->getAddr() - pioAddr; - int cpu_id = pkt->req->contextId(); + ContextID cpu_id = pkt->req->contextId(); DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr); assert(cpu_id >= 0); assert(cpu_id < CPU_MAX); diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc index f4a3e8c3f..71d1d3bb6 100644 --- a/src/dev/arm/vgic.cc +++ b/src/dev/arm/vgic.cc @@ -90,7 +90,7 @@ VGic::readVCpu(PacketPtr pkt) { Addr daddr = pkt->getAddr() - vcpuAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < VGIC_CPU_MAX); struct vcpuIntData *vid = &vcpuData[ctx_id]; @@ -134,7 +134,7 @@ VGic::readCtrl(PacketPtr pkt) { Addr daddr = pkt->getAddr() - hvAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr); @@ -228,7 +228,7 @@ VGic::writeVCpu(PacketPtr pkt) { Addr daddr = pkt->getAddr() - vcpuAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < VGIC_CPU_MAX); struct vcpuIntData *vid = &vcpuData[ctx_id]; @@ -275,7 +275,7 @@ VGic::writeCtrl(PacketPtr pkt) { Addr daddr = pkt->getAddr() - hvAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get()); @@ -380,7 +380,7 @@ VGic::unPostMaintInt(uint32_t cpu) * This may raise a maintenance interrupt. */ void -VGic::updateIntState(int ctx_id) +VGic::updateIntState(ContextID ctx_id) { // @todo This should update APRs! diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh index ac88f842f..d44afd7a9 100644 --- a/src/dev/arm/vgic.hh +++ b/src/dev/arm/vgic.hh @@ -222,7 +222,7 @@ class VGic : public PioDevice Tick writeVCpu(PacketPtr pkt); Tick writeCtrl(PacketPtr pkt); - void updateIntState(int ctx_id); + void updateIntState(ContextID ctx_id); uint32_t getMISR(struct vcpuIntData *vid); void postVInt(uint32_t cpu, Tick when); void unPostVInt(uint32_t cpu); diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index d4a3f19b3..a17f50864 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -152,7 +152,7 @@ Device::getEthPort(const std::string &if_name, int idx) void -Device::prepareIO(int cpu, int index) +Device::prepareIO(ContextID cpu, int index) { int size = virtualRegs.size(); if (index > size) @@ -165,7 +165,7 @@ Device::prepareIO(int cpu, int index) //add stats for average number of vnics busy void -Device::prepareRead(int cpu, int index) +Device::prepareRead(ContextID cpu, int index) { using namespace Regs; prepareIO(cpu, index); @@ -206,7 +206,7 @@ Device::prepareRead(int cpu, int index) } void -Device::prepareWrite(int cpu, int index) +Device::prepareWrite(ContextID cpu, int index) { prepareIO(cpu, index); } @@ -220,7 +220,7 @@ Device::read(PacketPtr pkt) assert(config.command & PCI_CMD_MSE); assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); - int cpu = pkt->req->contextId(); + ContextID cpu = pkt->req->contextId(); Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -270,7 +270,7 @@ Device::read(PacketPtr pkt) * IPR read of device register Fault -Device::iprRead(Addr daddr, int cpu, uint64_t &result) +Device::iprRead(Addr daddr, ContextID cpu, uint64_t &result) { if (!regValid(daddr)) panic("invalid address: da=%#x", daddr); @@ -305,7 +305,7 @@ Device::write(PacketPtr pkt) assert(config.command & PCI_CMD_MSE); assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); - int cpu = pkt->req->contextId(); + ContextID cpu = pkt->req->contextId(); Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh index 69b81b1b2..f0645a807 100644 --- a/src/dev/sinic.hh +++ b/src/dev/sinic.hh @@ -273,10 +273,10 @@ class Device : public Base virtual Tick write(PacketPtr pkt); virtual void drainResume() M5_ATTR_OVERRIDE; - void prepareIO(int cpu, int index); - void prepareRead(int cpu, int index); - void prepareWrite(int cpu, int index); - // Fault iprRead(Addr daddr, int cpu, uint64_t &result); + void prepareIO(ContextID cpu, int index); + void prepareRead(ContextID cpu, int index); + void prepareWrite(ContextID cpu, int index); + // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result); /** * Statistics diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc index bee0323c8..c8462b9be 100644 --- a/src/dev/sparc/iob.cc +++ b/src/dev/sparc/iob.cc @@ -118,7 +118,7 @@ void Iob::readJBus(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobJBusAddr; - int cpuid = pkt->req->contextId(); + ContextID cpuid = pkt->req->contextId(); int index; uint64_t data; @@ -233,7 +233,7 @@ void Iob::writeJBus(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobJBusAddr; - int cpuid = pkt->req->contextId(); + ContextID cpuid = pkt->req->contextId(); int index; uint64_t data; -- cgit v1.2.3