From 7eccb1b779cb6458ed78ba73f2fdabe94fa805b3 Mon Sep 17 00:00:00 2001 From: Akash Bagdia Date: Thu, 27 Jun 2013 05:49:49 -0400 Subject: config: Remove redundant explicit setting of default clocks This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour. The main motivation for these simplifications is to ease the introduction of clock domains. --- src/dev/CopyEngine.py | 2 -- src/dev/arm/RealView.py | 2 -- 2 files changed, 4 deletions(-) (limited to 'src/dev') diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py index 68332e0a0..d56294d66 100644 --- a/src/dev/CopyEngine.py +++ b/src/dev/CopyEngine.py @@ -53,8 +53,6 @@ class CopyEngine(PciDevice): ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device") XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported") - # Override the default clock - clock = '500MHz' latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed") latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such") diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index ab994b6f0..5c2768fb9 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -118,8 +118,6 @@ class CpuLocalTimer(BasicPioDevice): gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") - # Override the default clock - clock = '1GHz' class PL031(AmbaIntDevice): type = 'PL031' -- cgit v1.2.3