From 7f25332af078d0843b8f9e343def59c22d12c6a0 Mon Sep 17 00:00:00 2001 From: Chun-Chen TK Hsu Date: Tue, 1 Oct 2019 21:22:27 +0800 Subject: arch-arm: Refactor code to check if gic is GicV2 Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is only meanful to GicV2. Test: Boot Android P successfully with the following command: M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel $PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img --kernel-init "/init" --cpu-type fastmodel --machine-type VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0 --mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2 android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5 androidboot.selinux=permissive audit=0 cma=128M" Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339 Tested-by: kokoro Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini --- src/dev/arm/base_gic.hh | 4 ++++ src/dev/arm/gic_v2.cc | 6 ++++++ src/dev/arm/gic_v2.hh | 2 ++ src/dev/arm/gic_v3.cc | 7 +++++++ src/dev/arm/gic_v3.hh | 1 + 5 files changed, 20 insertions(+) (limited to 'src/dev') diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh index 7c0cc0edc..3d7a57924 100644 --- a/src/dev/arm/base_gic.hh +++ b/src/dev/arm/base_gic.hh @@ -65,6 +65,7 @@ class BaseGic : public PioDevice { public: typedef BaseGicParams Params; + enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 }; BaseGic(const Params *p); virtual ~BaseGic(); @@ -107,6 +108,9 @@ class BaseGic : public PioDevice return (ArmSystem *) sys; } + /** Check if version supported */ + virtual bool supportsVersion(GicVersion version) = 0; + protected: /** Platform this GIC belongs to. */ Platform *platform; diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index fa480a222..20bd01570 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -950,6 +950,12 @@ GicV2::postFiq(uint32_t cpu, Tick when) } } +bool +GicV2::supportsVersion(GicVersion version) +{ + return version == GicVersion::GIC_V2; +} + void GicV2::postDelayedFiq(uint32_t cpu) { diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh index 410414075..15cb89e0a 100644 --- a/src/dev/arm/gic_v2.hh +++ b/src/dev/arm/gic_v2.hh @@ -475,6 +475,8 @@ class GicV2 : public BaseGic, public BaseGicRegisters void sendPPInt(uint32_t num, uint32_t cpu) override; void clearPPInt(uint32_t num, uint32_t cpu) override; + bool supportsVersion(GicVersion version) override; + protected: /** Handle a read to the distributor portion of the GIC * @param pkt packet to respond to diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc index ba0a8ee63..e9c2fbcfe 100644 --- a/src/dev/arm/gic_v3.cc +++ b/src/dev/arm/gic_v3.cc @@ -209,6 +209,13 @@ Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type) platform->intrctrl->post(cpu, int_type, 0); } +bool +Gicv3::supportsVersion(GicVersion version) +{ + return (version == GicVersion::GIC_V3) || + (version == GicVersion::GIC_V4 && params()->gicv4); +} + void Gicv3::deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type) { diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh index 89a8abec0..e0212ee61 100644 --- a/src/dev/arm/gic_v3.hh +++ b/src/dev/arm/gic_v3.hh @@ -125,6 +125,7 @@ class Gicv3 : public BaseGic void serialize(CheckpointOut & cp) const override; void unserialize(CheckpointIn & cp) override; Tick write(PacketPtr pkt) override; + bool supportsVersion(GicVersion version) override; public: -- cgit v1.2.3