From bba265ccd8f50376ac2f148c4dd85b9eca30e8da Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 16 Aug 2007 16:49:05 -0400 Subject: PCI: Move PCI Configuration data into devices now that we can inherit parameters. --HG-- extra : convert_revision : bd2214b28fb46a9a9e9e204e0539be33acb548ad --- src/dev/Ethernet.py | 52 +++++++++++-------------- src/dev/Ide.py | 24 ++++++------ src/dev/Pci.py | 35 +++++++++-------- src/dev/pcidev.cc | 107 ++++++++++++++++++++++------------------------------ src/dev/pcidev.hh | 36 ++---------------- 5 files changed, 101 insertions(+), 153 deletions(-) (limited to 'src/dev') diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py index bef9a0a20..2beb0d537 100644 --- a/src/dev/Ethernet.py +++ b/src/dev/Ethernet.py @@ -29,7 +29,7 @@ from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from Pci import PciDevice, PciConfigData +from Pci import PciDevice class EtherObject(SimObject): type = 'EtherObject' @@ -79,8 +79,6 @@ class IGbE(EtherDevice): tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") clock = Param.Clock('500MHz', "Clock speed of the device") - -class IGbEPciData(PciConfigData): VendorID = 0x8086 DeviceID = 0x1075 SubsystemID = 0x1008 @@ -125,7 +123,13 @@ class EtherDevBase(EtherDevice): tx_thread = Param.Bool(False, "dedicated kernel threads for receive") rss = Param.Bool(False, "Receive Side Scaling") -class NSGigEPciData(PciConfigData): +class NSGigE(EtherDevBase): + type = 'NSGigE' + + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + VendorID = 0x100B DeviceID = 0x0022 Status = 0x0290 @@ -145,17 +149,25 @@ class NSGigEPciData(PciConfigData): BAR0Size = '256B' BAR1Size = '4kB' -class NSGigE(EtherDevBase): - type = 'NSGigE' - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - configdata = NSGigEPciData() +class Sinic(EtherDevBase): + type = 'Sinic' + cxx_namespace = 'Sinic' + cxx_class = 'Device' + rx_max_copy = Param.MemorySize('1514B', "rx max copy") + tx_max_copy = Param.MemorySize('16kB', "tx max copy") + rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") + rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") + rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") + tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") + tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") + virtual_count = Param.UInt32(1, "Virtualized SINIC") + zero_copy = Param.Bool(False, "Zero copy receive") + delay_copy = Param.Bool(False, "Delayed copy transmit") + virtual_addr = Param.Bool(False, "Virtual addressing") -class SinicPciData(PciConfigData): VendorID = 0x1291 DeviceID = 0x1293 Status = 0x0290 @@ -174,22 +186,4 @@ class SinicPciData(PciConfigData): InterruptPin = 0x01 BAR0Size = '64kB' -class Sinic(EtherDevBase): - type = 'Sinic' - cxx_namespace = 'Sinic' - cxx_class = 'Device' - - rx_max_copy = Param.MemorySize('1514B', "rx max copy") - tx_max_copy = Param.MemorySize('16kB', "tx max copy") - rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") - rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") - rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") - tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") - tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") - virtual_count = Param.UInt32(1, "Virtualized SINIC") - zero_copy = Param.Bool(False, "Zero copy receive") - delay_copy = Param.Bool(False, "Delayed copy transmit") - virtual_addr = Param.Bool(False, "Virtual addressing") - - configdata = SinicPciData() diff --git a/src/dev/Ide.py b/src/dev/Ide.py index 6bbaad00e..a396c9690 100644 --- a/src/dev/Ide.py +++ b/src/dev/Ide.py @@ -28,11 +28,20 @@ from m5.SimObject import SimObject from m5.params import * -from Pci import PciDevice, PciConfigData +from Pci import PciDevice class IdeID(Enum): vals = ['master', 'slave'] -class IdeControllerPciData(PciConfigData): +class IdeDisk(SimObject): + type = 'IdeDisk' + delay = Param.Latency('1us', "Fixed disk delay in microseconds") + driveID = Param.IdeID('master', "Drive ID") + image = Param.DiskImage("Disk image") + +class IdeController(PciDevice): + type = 'IdeController' + disks = VectorParam.IdeDisk("IDE disks attached to this controller") + VendorID = 0x8086 DeviceID = 0x7111 Command = 0x0 @@ -55,14 +64,3 @@ class IdeControllerPciData(PciConfigData): BAR3Size = '4B' BAR4Size = '16B' -class IdeDisk(SimObject): - type = 'IdeDisk' - delay = Param.Latency('1us', "Fixed disk delay in microseconds") - driveID = Param.IdeID('master', "Drive ID") - image = Param.DiskImage("Disk image") - -class IdeController(PciDevice): - type = 'IdeController' - disks = VectorParam.IdeDisk("IDE disks attached to this controller") - - configdata =IdeControllerPciData() diff --git a/src/dev/Pci.py b/src/dev/Pci.py index b2c013f41..b50e1b15c 100644 --- a/src/dev/Pci.py +++ b/src/dev/Pci.py @@ -31,8 +31,23 @@ from m5.params import * from m5.proxy import * from Device import BasicPioDevice, DmaDevice, PioDevice -class PciConfigData(SimObject): - type = 'PciConfigData' +class PciConfigAll(PioDevice): + type = 'PciConfigAll' + pio_latency = Param.Tick(1, "Programmed IO latency in simticks") + bus = Param.UInt8(0x00, "PCI bus to act as config space for") + size = Param.MemorySize32('16MB', "Size of config space") + + +class PciDevice(DmaDevice): + type = 'PciDevice' + abstract = True + config = Port(Self.pio.peerObj.port, "PCI configuration space port") + pci_bus = Param.Int("PCI bus") + pci_dev = Param.Int("PCI device number") + pci_func = Param.Int("PCI function code") + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") + config_latency = Param.Latency('20ns', "Config read or write latency") + VendorID = Param.UInt16("Vendor ID") DeviceID = Param.UInt16("Device ID") Command = Param.UInt16(0, "Command") @@ -68,20 +83,4 @@ class PciConfigData(SimObject): MaximumLatency = Param.UInt8(0x00, "Maximum Latency") MinimumGrant = Param.UInt8(0x00, "Minimum Grant") -class PciConfigAll(PioDevice): - type = 'PciConfigAll' - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") - bus = Param.UInt8(0x00, "PCI bus to act as config space for") - size = Param.MemorySize32('16MB', "Size of config space") - -class PciDevice(DmaDevice): - type = 'PciDevice' - abstract = True - config = Port(Self.pio.peerObj.port, "PCI configuration space port") - pci_bus = Param.Int("PCI bus") - pci_dev = Param.Int("PCI device number") - pci_func = Param.Int("PCI function code") - pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") - configdata = Param.PciConfigData(Parent.any, "PCI Config data") - config_latency = Param.Latency('20ns', "Config read or write latency") diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index 6c67e324c..aa532414c 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -48,7 +48,6 @@ #include "dev/alpha/tsunamireg.h" #include "mem/packet.hh" #include "mem/packet_access.hh" -#include "params/PciConfigData.hh" #include "sim/byteswap.hh" #include "sim/core.hh" @@ -82,21 +81,57 @@ PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp, PciDev::PciDev(const Params *p) - : DmaDevice(p), plat(p->platform), configData(p->configdata), - pioDelay(p->pio_latency), configDelay(p->config_latency), - configPort(NULL) + : DmaDevice(p), plat(p->platform), pioDelay(p->pio_latency), + configDelay(p->config_latency), configPort(NULL) { - // copy the config data from the PciConfigData object - if (configData) { - memcpy(config.data, configData->config.data, sizeof(config.data)); - memcpy(BARSize, configData->BARSize, sizeof(BARSize)); - } else - panic("NULL pointer to configuration data"); + config.vendor = htole(p->VendorID); + config.device = htole(p->DeviceID); + config.command = htole(p->Command); + config.status = htole(p->Status); + config.revision = htole(p->Revision); + config.progIF = htole(p->ProgIF); + config.subClassCode = htole(p->SubClassCode); + config.classCode = htole(p->ClassCode); + config.cacheLineSize = htole(p->CacheLineSize); + config.latencyTimer = htole(p->LatencyTimer); + config.headerType = htole(p->HeaderType); + config.bist = htole(p->BIST); + + config.baseAddr[0] = htole(p->BAR0); + config.baseAddr[1] = htole(p->BAR1); + config.baseAddr[2] = htole(p->BAR2); + config.baseAddr[3] = htole(p->BAR3); + config.baseAddr[4] = htole(p->BAR4); + config.baseAddr[5] = htole(p->BAR5); + config.cardbusCIS = htole(p->CardbusCIS); + config.subsystemVendorID = htole(p->SubsystemVendorID); + config.subsystemID = htole(p->SubsystemID); + config.expansionROM = htole(p->ExpansionROM); + config.reserved0 = 0; + config.reserved1 = 0; + config.interruptLine = htole(p->InterruptLine); + config.interruptPin = htole(p->InterruptPin); + config.minimumGrant = htole(p->MinimumGrant); + config.maximumLatency = htole(p->MaximumLatency); + + BARSize[0] = p->BAR0Size; + BARSize[1] = p->BAR1Size; + BARSize[2] = p->BAR2Size; + BARSize[3] = p->BAR3Size; + BARSize[4] = p->BAR4Size; + BARSize[5] = p->BAR5Size; + + for (int i = 0; i < 6; ++i) { + uint32_t barsize = BARSize[i]; + if (barsize != 0 && !isPowerOf2(barsize)) { + fatal("BAR %d size %d is not a power of 2\n", i, BARSize[i]); + } + } memset(BARAddrs, 0, sizeof(BARAddrs)); plat->registerPciDevice(0, p->pci_dev, p->pci_func, - letoh(configData->config.interruptLine)); + letoh(config.interruptLine)); } void @@ -304,53 +339,3 @@ PciDev::unserialize(Checkpoint *cp, const std::string §ion) } -PciConfigData * -PciConfigDataParams::create() -{ - PciConfigData *data = new PciConfigData(name); - - data->config.vendor = htole(VendorID); - data->config.device = htole(DeviceID); - data->config.command = htole(Command); - data->config.status = htole(Status); - data->config.revision = htole(Revision); - data->config.progIF = htole(ProgIF); - data->config.subClassCode = htole(SubClassCode); - data->config.classCode = htole(ClassCode); - data->config.cacheLineSize = htole(CacheLineSize); - data->config.latencyTimer = htole(LatencyTimer); - data->config.headerType = htole(HeaderType); - data->config.bist = htole(BIST); - - data->config.baseAddr[0] = htole(BAR0); - data->config.baseAddr[1] = htole(BAR1); - data->config.baseAddr[2] = htole(BAR2); - data->config.baseAddr[3] = htole(BAR3); - data->config.baseAddr[4] = htole(BAR4); - data->config.baseAddr[5] = htole(BAR5); - data->config.cardbusCIS = htole(CardbusCIS); - data->config.subsystemVendorID = htole(SubsystemVendorID); - data->config.subsystemID = htole(SubsystemID); - data->config.expansionROM = htole(ExpansionROM); - data->config.interruptLine = htole(InterruptLine); - data->config.interruptPin = htole(InterruptPin); - data->config.minimumGrant = htole(MinimumGrant); - data->config.maximumLatency = htole(MaximumLatency); - - data->BARSize[0] = BAR0Size; - data->BARSize[1] = BAR1Size; - data->BARSize[2] = BAR2Size; - data->BARSize[3] = BAR3Size; - data->BARSize[4] = BAR4Size; - data->BARSize[5] = BAR5Size; - - for (int i = 0; i < 6; ++i) { - uint32_t barsize = data->BARSize[i]; - if (barsize != 0 && !isPowerOf2(barsize)) { - fatal("%s: BAR %d size %d is not a power of 2\n", - name, i, data->BARSize[i]); - } - } - - return data; -} diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index 6c72d1b15..a584a957d 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -52,30 +52,6 @@ #define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2); -/** - * This class encapulates the first 64 bytes of a singles PCI - * devices config space that in configured by the configuration file. - */ -class PciConfigData : public SimObject -{ - public: - /** - * Constructor to initialize the devices config space to 0. - */ - PciConfigData(const std::string &name) - : SimObject(name) - { - std::memset(config.data, 0, sizeof(config.data)); - std::memset(BARSize, 0, sizeof(BARSize)); - } - - /** The first 64 bytes */ - PCIConfig config; - - /** The size of the BARs */ - uint32_t BARSize[6]; -}; - /** * PCI device, base implementation is only config space. @@ -114,10 +90,7 @@ class PciDev : public DmaDevice } protected: - /** The current config space. Unlike the PciConfigData this is - * updated during simulation while continues to reflect what was - * in the config file. - */ + /** The current config space. */ PCIConfig config; /** The size of the BARs */ @@ -174,7 +147,6 @@ class PciDev : public DmaDevice protected: Platform *plat; - PciConfigData *configData; Tick pioDelay; Tick configDelay; PciConfigPort *configPort; @@ -202,15 +174,15 @@ class PciDev : public DmaDevice void intrPost() - { plat->postPciInt(letoh(configData->config.interruptLine)); } + { plat->postPciInt(letoh(config.interruptLine)); } void intrClear() - { plat->clearPciInt(letoh(configData->config.interruptLine)); } + { plat->clearPciInt(letoh(config.interruptLine)); } uint8_t interruptLine() - { return letoh(configData->config.interruptLine); } + { return letoh(config.interruptLine); } /** return the address ranges that this device responds to. * @params range_list range list to populate with ranges -- cgit v1.2.3