From d3bfc03688e164c02e9c25730ada11b669c01eda Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Tue, 14 Feb 2017 15:09:18 -0600 Subject: sim,kvm,arm: fix typos Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85 Reviewed-by: Andreas Sandberg --- src/dev/arm/gic_pl390.cc | 6 +++--- src/dev/arm/gic_pl390.hh | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'src/dev') diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc index 3c6fed712..e7dc8e907 100644 --- a/src/dev/arm/gic_pl390.cc +++ b/src/dev/arm/gic_pl390.cc @@ -542,7 +542,7 @@ Pl390::writeCpu(PacketPtr pkt) case GICC_EOIR: iar = pkt->get(); if (iar.ack_id < SGI_MAX) { - // Clear out the bit that corrseponds to the cleared int + // Clear out the bit that corresponds to the cleared int uint64_t clr_int = ULL(1) << (ctx + 8 * iar.cpu_id); if (!(cpuSgiActive[iar.ack_id] & clr_int) && !(cpuSgiActiveExt[ctx] & (1 << iar.ack_id))) @@ -709,7 +709,7 @@ Pl390::updateIntState(int hint) DPRINTF(GIC, "Checking for interrupt# %d \n",int_nm); /* Set current pending int as highest int for current cpu if the interrupt's priority higher than current priority - and if currrent cpu is the target (for mp configs only) + and if current cpu is the target (for mp configs only) */ if ((bits(getIntEnabled(cpu, x), y) &bits(getPendingInt(cpu, x), y)) && @@ -775,7 +775,7 @@ Pl390::updateRunPri() void Pl390::sendInt(uint32_t num) { - DPRINTF(Interrupt, "Received Interupt number %d, cpuTarget %#x: \n", + DPRINTF(Interrupt, "Received Interrupt number %d, cpuTarget %#x: \n", num, cpuTarget[num]); if ((cpuTarget[num] & (cpuTarget[num] - 1)) && !gem5ExtensionsEnabled) panic("Multiple targets for peripheral interrupts is not supported\n"); diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh index b1164f961..7c5511227 100644 --- a/src/dev/arm/gic_pl390.hh +++ b/src/dev/arm/gic_pl390.hh @@ -88,7 +88,7 @@ class Pl390 : public BaseGic GICC_BPR = 0x08, // binary point register GICC_IAR = 0x0C, // interrupt ack register GICC_EOIR = 0x10, // end of interrupt - GICC_RPR = 0x14, // runing priority + GICC_RPR = 0x14, // running priority GICC_HPPIR = 0x18, // highest pending interrupt GICC_ABPR = 0x1c, // aliased binary point GICC_IIDR = 0xfc, // cpu interface id register @@ -391,22 +391,22 @@ class Pl390 : public BaseGic void unserialize(CheckpointIn &cp) override; protected: - /** Handle a read to the distributor poriton of the GIC + /** Handle a read to the distributor portion of the GIC * @param pkt packet to respond to */ Tick readDistributor(PacketPtr pkt); - /** Handle a read to the cpu poriton of the GIC + /** Handle a read to the cpu portion of the GIC * @param pkt packet to respond to */ Tick readCpu(PacketPtr pkt); - /** Handle a write to the distributor poriton of the GIC + /** Handle a write to the distributor portion of the GIC * @param pkt packet to respond to */ Tick writeDistributor(PacketPtr pkt); - /** Handle a write to the cpu poriton of the GIC + /** Handle a write to the cpu portion of the GIC * @param pkt packet to respond to */ Tick writeCpu(PacketPtr pkt); -- cgit v1.2.3