From e533fad711fce66bf2e4a6669baeb8eaf02799e1 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Fri, 26 May 2006 14:17:33 -0400 Subject: Significant rework of Packet class interface: - new constructor guarantees initialization of most fields - flags track status of non-guaranteed fields (addr, size, src) - accessor functions (getAddr() etc.) check status on access - Command & Result classes are nested in Packet class scope - Command now built from vector of behavior bits - string version of Command for tracing - reinitFromRequest() and makeTimingResponse() encapsulate common manipulations of existing packets src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/timing.cc: src/dev/alpha_console.cc: src/dev/ide_ctrl.cc: src/dev/io_device.cc: src/dev/io_device.hh: src/dev/isa_fake.cc: src/dev/ns_gige.cc: src/dev/pciconfigall.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/dev/tsunami_io.cc: src/dev/tsunami_pchip.cc: src/dev/uart8250.cc: src/mem/bus.cc: src/mem/bus.hh: src/mem/physical.cc: src/mem/port.cc: src/mem/port.hh: src/mem/request.hh: Update for new Packet interface. --HG-- extra : convert_revision : 9973d09ea4fa61795f23772a7d3995fa4df5c269 --- src/dev/alpha_console.cc | 25 +++++++-------- src/dev/ide_ctrl.cc | 80 ++++++++++++++++++++++++------------------------ src/dev/io_device.cc | 59 +++++++++++++---------------------- src/dev/io_device.hh | 12 ++++---- src/dev/isa_fake.cc | 14 ++++----- src/dev/ns_gige.cc | 34 ++++++++++---------- src/dev/pciconfigall.cc | 30 +++++++++--------- src/dev/sinic.cc | 30 +++++++++--------- src/dev/tsunami_cchip.cc | 28 ++++++++--------- src/dev/tsunami_io.cc | 36 +++++++++++----------- src/dev/tsunami_pchip.cc | 24 +++++++-------- src/dev/uart8250.cc | 20 ++++++------ 12 files changed, 189 insertions(+), 203 deletions(-) (limited to 'src/dev') diff --git a/src/dev/alpha_console.cc b/src/dev/alpha_console.cc index f24c09844..0b4bb048c 100644 --- a/src/dev/alpha_console.cc +++ b/src/dev/alpha_console.cc @@ -95,15 +95,15 @@ AlphaConsole::read(Packet *pkt) * machine dependent address swizzle is required? */ - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); pkt->time += pioDelay; - Addr daddr = pkt->addr - pioAddr; + Addr daddr = pkt->getAddr() - pioAddr; pkt->allocate(); - switch (pkt->size) + switch (pkt->getSize()) { case sizeof(uint32_t): switch (daddr) @@ -124,7 +124,7 @@ AlphaConsole::read(Packet *pkt) /* Old console code read in everyting as a 32bit int * we now break that for better error checking. */ - pkt->result = BadAddress; + pkt->result = Packet::BadAddress; } DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, pkt->get()); @@ -181,9 +181,10 @@ AlphaConsole::read(Packet *pkt) pkt->get()); break; default: - pkt->result = BadAddress; + pkt->result = Packet::BadAddress; } - if (pkt->result == Unknown) pkt->result = Success; + if (pkt->result == Packet::Unknown) + pkt->result = Packet::Success; return pioDelay; } @@ -192,12 +193,12 @@ AlphaConsole::write(Packet *pkt) { pkt->time += pioDelay; - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - Addr daddr = pkt->addr - pioAddr; + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); + Addr daddr = pkt->getAddr() - pioAddr; uint64_t val = pkt->get(); - assert(pkt->size == sizeof(uint64_t)); + assert(pkt->getSize() == sizeof(uint64_t)); switch (daddr) { case offsetof(AlphaAccess, diskUnit): @@ -240,7 +241,7 @@ AlphaConsole::write(Packet *pkt) panic("Unknown 64bit access, %#x\n", daddr); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc index cedd5c53e..eb03d5db8 100644 --- a/src/dev/ide_ctrl.cc +++ b/src/dev/ide_ctrl.cc @@ -432,19 +432,19 @@ IdeController::read(Packet *pkt) pkt->time += pioDelay; pkt->allocate(); - if (pkt->size != 1 && pkt->size != 2 && pkt->size !=4) - panic("Bad IDE read size: %d\n", pkt->size); + if (pkt->getSize() != 1 && pkt->getSize() != 2 && pkt->getSize() !=4) + panic("Bad IDE read size: %d\n", pkt->getSize()); - parseAddr(pkt->addr, offset, channel, reg_type); + parseAddr(pkt->getAddr(), offset, channel, reg_type); if (!io_enabled) { - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } switch (reg_type) { case BMI_BLOCK: - switch (pkt->size) { + switch (pkt->getSize()) { case sizeof(uint8_t): pkt->set(bmi_regs.data[offset]); break; @@ -455,7 +455,7 @@ IdeController::read(Packet *pkt) pkt->set(*(uint32_t*)&bmi_regs.data[offset]); break; default: - panic("IDE read of BMI reg invalid size: %#x\n", pkt->size); + panic("IDE read of BMI reg invalid size: %#x\n", pkt->getSize()); } break; @@ -470,7 +470,7 @@ IdeController::read(Packet *pkt) switch (offset) { case DATA_OFFSET: - switch (pkt->size) { + switch (pkt->getSize()) { case sizeof(uint16_t): disks[disk]->read(offset, reg_type, pkt->getPtr()); break; @@ -482,30 +482,30 @@ IdeController::read(Packet *pkt) break; default: - panic("IDE read of data reg invalid size: %#x\n", pkt->size); + panic("IDE read of data reg invalid size: %#x\n", pkt->getSize()); } break; default: - if (pkt->size == sizeof(uint8_t)) { + if (pkt->getSize() == sizeof(uint8_t)) { disks[disk]->read(offset, reg_type, pkt->getPtr()); } else - panic("IDE read of command reg of invalid size: %#x\n", pkt->size); + panic("IDE read of command reg of invalid size: %#x\n", pkt->getSize()); } break; default: panic("IDE controller read of unknown register block type!\n"); } - if (pkt->size == 1) + if (pkt->getSize() == 1) DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n", - offset, pkt->size, (uint32_t)pkt->get()); - else if (pkt->size == 2) + offset, pkt->getSize(), (uint32_t)pkt->get()); + else if (pkt->getSize() == 2) DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n", - offset, pkt->size, pkt->get()); + offset, pkt->getSize(), pkt->get()); else DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n", - offset, pkt->size, pkt->get()); + offset, pkt->getSize(), pkt->get()); - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -520,10 +520,10 @@ IdeController::write(Packet *pkt) pkt->time += pioDelay; - parseAddr(pkt->addr, offset, channel, reg_type); + parseAddr(pkt->getAddr(), offset, channel, reg_type); if (!io_enabled) { - pkt->result = Success; + pkt->result = Packet::Success; DPRINTF(IdeCtrl, "io not enabled\n"); return pioDelay; } @@ -531,7 +531,7 @@ IdeController::write(Packet *pkt) switch (reg_type) { case BMI_BLOCK: if (!bm_enabled) { - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -539,8 +539,8 @@ IdeController::write(Packet *pkt) // Bus master IDE command register case BMIC1: case BMIC0: - if (pkt->size != sizeof(uint8_t)) - panic("Invalid BMIC write size: %x\n", pkt->size); + if (pkt->getSize() != sizeof(uint8_t)) + panic("Invalid BMIC write size: %x\n", pkt->getSize()); // select the current disk based on DEV bit disk = getDisk(channel); @@ -595,8 +595,8 @@ IdeController::write(Packet *pkt) // Bus master IDE status register case BMIS0: case BMIS1: - if (pkt->size != sizeof(uint8_t)) - panic("Invalid BMIS write size: %x\n", pkt->size); + if (pkt->getSize() != sizeof(uint8_t)) + panic("Invalid BMIS write size: %x\n", pkt->getSize()); oldVal = bmi_regs.chan[channel].bmis; newVal = pkt->get(); @@ -622,22 +622,22 @@ IdeController::write(Packet *pkt) case BMIDTP0: case BMIDTP1: { - if (pkt->size != sizeof(uint32_t)) - panic("Invalid BMIDTP write size: %x\n", pkt->size); + if (pkt->getSize() != sizeof(uint32_t)) + panic("Invalid BMIDTP write size: %x\n", pkt->getSize()); bmi_regs.chan[channel].bmidtp = htole(pkt->get() & ~0x3); } break; default: - if (pkt->size != sizeof(uint8_t) && - pkt->size != sizeof(uint16_t) && - pkt->size != sizeof(uint32_t)) + if (pkt->getSize() != sizeof(uint8_t) && + pkt->getSize() != sizeof(uint16_t) && + pkt->getSize() != sizeof(uint32_t)) panic("IDE controller write of invalid write size: %x\n", - pkt->size); + pkt->getSize()); // do a default copy of data into the registers - memcpy(&bmi_regs.data[offset], pkt->getPtr(), pkt->size); + memcpy(&bmi_regs.data[offset], pkt->getPtr(), pkt->getSize()); } break; case COMMAND_BLOCK: @@ -654,7 +654,7 @@ IdeController::write(Packet *pkt) switch (offset) { case DATA_OFFSET: - switch (pkt->size) { + switch (pkt->getSize()) { case sizeof(uint16_t): disks[disk]->write(offset, reg_type, pkt->getPtr()); break; @@ -665,32 +665,32 @@ IdeController::write(Packet *pkt) sizeof(uint16_t)); break; default: - panic("IDE write of data reg invalid size: %#x\n", pkt->size); + panic("IDE write of data reg invalid size: %#x\n", pkt->getSize()); } break; default: - if (pkt->size == sizeof(uint8_t)) { + if (pkt->getSize() == sizeof(uint8_t)) { disks[disk]->write(offset, reg_type, pkt->getPtr()); } else - panic("IDE write of command reg of invalid size: %#x\n", pkt->size); + panic("IDE write of command reg of invalid size: %#x\n", pkt->getSize()); } break; default: panic("IDE controller write of unknown register block type!\n"); } - if (pkt->size == 1) + if (pkt->getSize() == 1) DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n", - offset, pkt->size, (uint32_t)pkt->get()); - else if (pkt->size == 2) + offset, pkt->getSize(), (uint32_t)pkt->get()); + else if (pkt->getSize() == 2) DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n", - offset, pkt->size, pkt->get()); + offset, pkt->getSize(), pkt->get()); else DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n", - offset, pkt->size, pkt->get()); + offset, pkt->getSize(), pkt->get()); - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 28b50f9e8..87fdbb765 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -67,7 +67,7 @@ PioPort::recvRetry() void PioPort::SendEvent::process() { - if (port->Port::sendTiming(packet) == Success) + if (port->Port::sendTiming(packet)) return; port->transmitList.push_back(packet); @@ -79,9 +79,9 @@ PioPort::recvTiming(Packet *pkt) { device->recvAtomic(pkt); // turn packet around to go back to requester - pkt->dest = pkt->src; + pkt->makeTimingResponse(); sendTiming(pkt, pkt->time - pkt->req->getTime()); - return Success; + return true; } PioDevice::~PioDevice() @@ -116,7 +116,7 @@ DmaPort::recvTiming(Packet *pkt) { if (pkt->senderState) { DmaReqState *state; - state = (DmaReqState*)pkt->senderState; + state = dynamic_cast(pkt->senderState); state->completionEvent->schedule(pkt->time - pkt->req->getTime()); delete pkt->req; delete pkt; @@ -125,7 +125,7 @@ DmaPort::recvTiming(Packet *pkt) delete pkt; } - return Success; + return Packet::Success; } DmaDevice::DmaDevice(Params *p) @@ -135,7 +135,7 @@ DmaDevice::DmaDevice(Params *p) void DmaPort::SendEvent::process() { - if (port->Port::sendTiming(packet) == Success) + if (port->Port::sendTiming(packet)) return; port->transmitList.push_back(packet); @@ -148,54 +148,39 @@ DmaPort::recvRetry() transmitList.pop_front(); return pkt; } + + void -DmaPort::dmaAction(Command cmd, Addr addr, int size, Event *event, - uint8_t *data) +DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, + uint8_t *data) { - assert(event); int prevSize = 0; - Packet basePkt; - Request baseReq(false); - - basePkt.flags = 0; - basePkt.coherence = NULL; - basePkt.senderState = NULL; - basePkt.dest = Packet::Broadcast; - basePkt.cmd = cmd; - basePkt.result = Unknown; - basePkt.req = NULL; -// baseReq.nicReq = true; - baseReq.setTime(curTick); for (ChunkGenerator gen(addr, size, peerBlockSize()); !gen.done(); gen.next()) { - Packet *pkt = new Packet(basePkt); - Request *req = new Request(baseReq); - pkt->addr = gen.addr(); - pkt->size = gen.size(); - pkt->req = req; - pkt->req->setPaddr(pkt->addr); - pkt->req->setSize(pkt->size); + Request *req = new Request(false); + req->setPaddr(gen.addr()); + req->setSize(gen.size()); + req->setTime(curTick); + Packet *pkt = new Packet(req, cmd, Packet::Broadcast); + // Increment the data pointer on a write if (data) pkt->dataStatic(data + prevSize) ; - prevSize += pkt->size; + + prevSize += gen.size(); + // Set the last bit of the dma as the final packet for this dma // and set it's completion event. if (prevSize == size) { - DmaReqState *state = new DmaReqState(event, true); - - pkt->senderState = (void*)state; + pkt->senderState = new DmaReqState(event, true); } assert(pendingCount >= 0); pendingCount++; sendDma(pkt); } - // since this isn't getting used and we want a check to make sure that all - // packets had data in them at some point. - basePkt.dataStatic((uint8_t*)NULL); } @@ -208,12 +193,12 @@ DmaPort::sendDma(Packet *pkt) /* MemState state = device->platform->system->memState; if (state == Timing) { - if (sendTiming(pkt) == Failure) + if (!sendTiming(pkt)) transmitList.push_back(&packet); } else if (state == Atomic) {*/ sendAtomic(pkt); if (pkt->senderState) { - DmaReqState *state = (DmaReqState*)pkt->senderState; + DmaReqState *state = dynamic_cast(pkt->senderState); state->completionEvent->schedule(curTick + (pkt->time - pkt->req->getTime()) +1); } pendingCount--; diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index 6efa9ef63..74730ad92 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -115,7 +115,7 @@ class PioPort : public Port }; -struct DmaReqState +struct DmaReqState : public Packet::SenderState { Event *completionEvent; bool final; @@ -173,8 +173,8 @@ class DmaPort : public Port public: DmaPort(DmaDevice *dev, Platform *p); - void dmaAction(Command cmd, Addr addr, int size, Event *event, - uint8_t *data = NULL); + void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, + uint8_t *data = NULL); bool dmaPending() { return pendingCount > 0; } @@ -207,7 +207,7 @@ class PioDevice : public MemObject /** As far as the devices are concerned they only accept atomic transactions * which are converted to either a write or a read. */ Tick recvAtomic(Packet *pkt) - { return pkt->cmd == Read ? this->read(pkt) : this->write(pkt); } + { return pkt->isRead() ? this->read(pkt) : this->write(pkt); } /** Pure virtual function that the device must implement. Called when a read * command is recieved by the port. @@ -305,10 +305,10 @@ class DmaDevice : public PioDevice virtual ~DmaDevice(); void dmaWrite(Addr addr, int size, Event *event, uint8_t *data) - { dmaPort->dmaAction(Write, addr, size, event, data) ; } + { dmaPort->dmaAction(Packet::WriteReq, addr, size, event, data) ; } void dmaRead(Addr addr, int size, Event *event, uint8_t *data = NULL) - { dmaPort->dmaAction(Read, addr, size, event, data); } + { dmaPort->dmaAction(Packet::ReadReq, addr, size, event, data); } bool dmaPending() { return dmaPort->dmaPending(); } diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc index 9717226b7..c303ffc30 100644 --- a/src/dev/isa_fake.cc +++ b/src/dev/isa_fake.cc @@ -51,14 +51,14 @@ IsaFake::IsaFake(Params *p) Tick IsaFake::read(Packet *pkt) { - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); pkt->time += pioDelay; - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->addr, pkt->size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); - switch (pkt->size) { + switch (pkt->getSize()) { pkt->set(0xFFFFFFFFFFFFFFFFULL); break; case sizeof(uint32_t): @@ -73,7 +73,7 @@ IsaFake::read(Packet *pkt) default: panic("invalid access size(?) for PCI configspace!\n"); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -81,8 +81,8 @@ Tick IsaFake::write(Packet *pkt) { pkt->time += pioDelay; - DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->addr, pkt->size); - pkt->result = Success; + DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 5e27db58d..963675847 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -496,9 +496,9 @@ NSGigE::read(Packet *pkt) pkt->allocate(); //The mask is to give you only the offset into the device register file - Addr daddr = pkt->addr & 0xfff; + Addr daddr = pkt->getAddr() & 0xfff; DPRINTF(EthernetPIO, "read da=%#x pa=%#x size=%d\n", - daddr, pkt->addr, pkt->size); + daddr, pkt->getAddr(), pkt->getSize()); // there are some reserved registers, you can see ns_gige_reg.h and @@ -506,25 +506,25 @@ NSGigE::read(Packet *pkt) if (daddr > LAST && daddr <= RESERVED) { panic("Accessing reserved register"); } else if (daddr > RESERVED && daddr <= 0x3FC) { - if (pkt->size == sizeof(uint8_t)) + if (pkt->getSize() == sizeof(uint8_t)) readConfig(daddr & 0xff, pkt->getPtr()); - if (pkt->size == sizeof(uint16_t)) + if (pkt->getSize() == sizeof(uint16_t)) readConfig(daddr & 0xff, pkt->getPtr()); - if (pkt->size == sizeof(uint32_t)) + if (pkt->getSize() == sizeof(uint32_t)) readConfig(daddr & 0xff, pkt->getPtr()); - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } else if (daddr >= MIB_START && daddr <= MIB_END) { // don't implement all the MIB's. hopefully the kernel // doesn't actually DEPEND upon their values // MIB are just hardware stats keepers pkt->set(0); - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } else if (daddr > 0x3FC) panic("Something is messed up!\n"); - assert(pkt->size == sizeof(uint32_t)); + assert(pkt->getSize() == sizeof(uint32_t)); uint32_t ® = *pkt->getPtr(); uint16_t rfaddr; @@ -715,7 +715,7 @@ NSGigE::read(Packet *pkt) DPRINTF(EthernetPIO, "read from %#x: data=%d data=%#x\n", daddr, reg, reg); - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -724,27 +724,27 @@ NSGigE::write(Packet *pkt) { assert(ioEnable); - Addr daddr = pkt->addr & 0xfff; + Addr daddr = pkt->getAddr() & 0xfff; DPRINTF(EthernetPIO, "write da=%#x pa=%#x size=%d\n", - daddr, pkt->addr, pkt->size); + daddr, pkt->getAddr(), pkt->getSize()); pkt->time += pioDelay; if (daddr > LAST && daddr <= RESERVED) { panic("Accessing reserved register"); } else if (daddr > RESERVED && daddr <= 0x3FC) { - if (pkt->size == sizeof(uint8_t)) + if (pkt->getSize() == sizeof(uint8_t)) writeConfig(daddr & 0xff, pkt->get()); - if (pkt->size == sizeof(uint16_t)) + if (pkt->getSize() == sizeof(uint16_t)) writeConfig(daddr & 0xff, pkt->get()); - if (pkt->size == sizeof(uint32_t)) + if (pkt->getSize() == sizeof(uint32_t)) writeConfig(daddr & 0xff, pkt->get()); - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } else if (daddr > 0x3FC) panic("Something is messed up!\n"); - if (pkt->size == sizeof(uint32_t)) { + if (pkt->getSize() == sizeof(uint32_t)) { uint32_t reg = pkt->get(); uint16_t rfaddr; @@ -1131,7 +1131,7 @@ NSGigE::write(Packet *pkt) } else { panic("Invalid Request Size"); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/pciconfigall.cc b/src/dev/pciconfigall.cc index f278a67cf..14a28e86d 100644 --- a/src/dev/pciconfigall.cc +++ b/src/dev/pciconfigall.cc @@ -91,10 +91,10 @@ PciConfigAll::startup() Tick PciConfigAll::read(Packet *pkt) { - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - Addr daddr = pkt->addr - pioAddr; + Addr daddr = pkt->getAddr() - pioAddr; int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; int reg = daddr & 0xFF; @@ -102,10 +102,10 @@ PciConfigAll::read(Packet *pkt) pkt->time += pioDelay; pkt->allocate(); - DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt->addr, daddr, - pkt->size); + DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt->getAddr(), daddr, + pkt->getSize()); - switch (pkt->size) { + switch (pkt->getSize()) { case sizeof(uint32_t): if (devices[device][func] == NULL) pkt->set(0xFFFFFFFF); @@ -127,7 +127,7 @@ PciConfigAll::read(Packet *pkt) default: panic("invalid access size(?) for PCI configspace!\n"); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -136,11 +136,11 @@ PciConfigAll::write(Packet *pkt) { pkt->time += pioDelay; - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - assert(pkt->size == sizeof(uint8_t) || pkt->size == sizeof(uint16_t) || - pkt->size == sizeof(uint32_t)); - Addr daddr = pkt->addr - pioAddr; + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); + assert(pkt->getSize() == sizeof(uint8_t) || pkt->getSize() == sizeof(uint16_t) || + pkt->getSize() == sizeof(uint32_t)); + Addr daddr = pkt->getAddr() - pioAddr; int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; @@ -150,9 +150,9 @@ PciConfigAll::write(Packet *pkt) panic("Attempting to write to config space on non-existant device\n"); DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n", - pkt->addr, pkt->size, pkt->get()); + pkt->getAddr(), pkt->getSize(), pkt->get()); - switch (pkt->size) { + switch (pkt->getSize()) { case sizeof(uint8_t): devices[device][func]->writeConfig(reg, pkt->get()); break; @@ -165,7 +165,7 @@ PciConfigAll::write(Packet *pkt) default: panic("invalid pci config write size\n"); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index df7e4d167..31fbc49aa 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -315,10 +315,10 @@ Tick Device::read(Packet *pkt) { assert(config.command & PCI_CMD_MSE); - assert(pkt->addr >= BARAddrs[0] && pkt->size < BARSize[0]); + assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); int cpu = pkt->req->getCpuNum(); - Addr daddr = pkt->addr - BARAddrs[0]; + Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -327,28 +327,28 @@ Device::read(Packet *pkt) if (!regValid(raddr)) panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d", - cpu, index, daddr, pkt->addr, pkt->size); + cpu, index, daddr, pkt->getAddr(), pkt->getSize()); const Regs::Info &info = regInfo(raddr); if (!info.read) panic("read %s (write only): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt->addr, pkt->size); + info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); panic("read %s (invalid size): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt->addr, pkt->size); + info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); prepareRead(cpu, index); uint64_t value = 0; - if (pkt->size == 4) { + if (pkt->getSize() == 4) { uint32_t reg = regData32(raddr); pkt->set(reg); value = reg; } - if (pkt->size == 8) { + if (pkt->getSize() == 8) { uint64_t reg = regData64(raddr); pkt->set(reg); value = reg; @@ -356,7 +356,7 @@ Device::read(Packet *pkt) DPRINTF(EthernetPIO, "read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n", - info.name, cpu, index, daddr, pkt->addr, pkt->size, value); + info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize(), value); // reading the interrupt status register has the side effect of // clearing it @@ -403,10 +403,10 @@ Tick Device::write(Packet *pkt) { assert(config.command & PCI_CMD_MSE); - assert(pkt->addr >= BARAddrs[0] && pkt->size < BARSize[0]); + assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); int cpu = pkt->req->getCpuNum(); - Addr daddr = pkt->addr - BARAddrs[0]; + Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -414,25 +414,25 @@ Device::write(Packet *pkt) if (!regValid(raddr)) panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d", - cpu, daddr, pkt->addr, pkt->size); + cpu, daddr, pkt->getAddr(), pkt->getSize()); const Regs::Info &info = regInfo(raddr); if (!info.write) panic("write %s (read only): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt->addr, pkt->size); + info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); - if (pkt->size != info.size) + if (pkt->getSize() != info.size) panic("write %s (invalid size): " "cpu=%d vnic=%d da=%#x pa=%#x size=%d", - info.name, cpu, index, daddr, pkt->addr, pkt->size); + info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize()); VirtualReg &vnic = virtualRegs[index]; DPRINTF(EthernetPIO, "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n", info.name, index, cpu, info.size == 4 ? pkt->get() : - pkt->get(), daddr, pkt->addr, pkt->size); + pkt->get(), daddr, pkt->getAddr(), pkt->getSize()); prepareWrite(cpu, index); diff --git a/src/dev/tsunami_cchip.cc b/src/dev/tsunami_cchip.cc index 7206a61bb..146321b9f 100644 --- a/src/dev/tsunami_cchip.cc +++ b/src/dev/tsunami_cchip.cc @@ -71,17 +71,17 @@ TsunamiCChip::TsunamiCChip(Params *p) Tick TsunamiCChip::read(Packet *pkt) { - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->addr, pkt->size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); pkt->time += pioDelay; - Addr regnum = (pkt->addr - pioAddr) >> 6; - Addr daddr = (pkt->addr - pioAddr); + Addr regnum = (pkt->getAddr() - pioAddr) >> 6; + Addr daddr = (pkt->getAddr() - pioAddr); pkt->allocate(); - switch (pkt->size) { + switch (pkt->getSize()) { case sizeof(uint64_t): if (daddr & TSDEV_CC_BDIMS) @@ -173,9 +173,9 @@ TsunamiCChip::read(Packet *pkt) panic("invalid access size(?) for tsunami register!\n"); } DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", - regnum, pkt->size, pkt->get()); + regnum, pkt->getSize(), pkt->get()); - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -185,14 +185,14 @@ TsunamiCChip::write(Packet *pkt) pkt->time += pioDelay; - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - Addr daddr = pkt->addr - pioAddr; - Addr regnum = (pkt->addr - pioAddr) >> 6 ; + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); + Addr daddr = pkt->getAddr() - pioAddr; + Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; - assert(pkt->size == sizeof(uint64_t)); + assert(pkt->getSize() == sizeof(uint64_t)); - DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->addr, pkt->get()); + DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get()); bool supportedWrite = false; @@ -362,7 +362,7 @@ TsunamiCChip::write(Packet *pkt) panic("default in cchip read reached, accessing 0x%x\n"); } // swtich(regnum) } // not BIG_TSUNAMI write - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/tsunami_io.cc b/src/dev/tsunami_io.cc index dd9feae99..7c649a84a 100644 --- a/src/dev/tsunami_io.cc +++ b/src/dev/tsunami_io.cc @@ -438,18 +438,18 @@ TsunamiIO::frequency() const Tick TsunamiIO::read(Packet *pkt) { - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); pkt->time += pioDelay; - Addr daddr = pkt->addr - pioAddr; + Addr daddr = pkt->getAddr() - pioAddr; - DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->addr, - pkt->size, daddr); + DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), + pkt->getSize(), daddr); pkt->allocate(); - if (pkt->size == sizeof(uint8_t)) { + if (pkt->getSize() == sizeof(uint8_t)) { switch(daddr) { // PIC1 mask read case TSDEV_PIC1_MASK: @@ -487,18 +487,18 @@ TsunamiIO::read(Packet *pkt) pkt->set(0x00); break; default: - panic("I/O Read - va%#x size %d\n", pkt->addr, pkt->size); + panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); } - } else if (pkt->size == sizeof(uint64_t)) { + } else if (pkt->getSize() == sizeof(uint64_t)) { if (daddr == TSDEV_PIC1_ISR) pkt->set(picr); else panic("I/O Read - invalid addr - va %#x size %d\n", - pkt->addr, pkt->size); + pkt->getAddr(), pkt->getSize()); } else { - panic("I/O Read - invalid size - va %#x size %d\n", pkt->addr, pkt->size); + panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -507,14 +507,14 @@ TsunamiIO::write(Packet *pkt) { pkt->time += pioDelay; - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - Addr daddr = pkt->addr - pioAddr; + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); + Addr daddr = pkt->getAddr() - pioAddr; DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", - pkt->addr, pkt->size, pkt->addr & 0xfff, (uint32_t)pkt->get()); + pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get()); - assert(pkt->size == sizeof(uint8_t)); + assert(pkt->getSize() == sizeof(uint8_t)); switch(daddr) { case TSDEV_PIC1_MASK: @@ -577,10 +577,10 @@ TsunamiIO::write(Packet *pkt) case TSDEV_CTRL_PORTB: break; default: - panic("I/O Write - va%#x size %d data %#x\n", pkt->addr, pkt->size, pkt->get()); + panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get()); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/tsunami_pchip.cc b/src/dev/tsunami_pchip.cc index 999278e37..c430ca0a0 100644 --- a/src/dev/tsunami_pchip.cc +++ b/src/dev/tsunami_pchip.cc @@ -67,17 +67,17 @@ TsunamiPChip::TsunamiPChip(Params *p) Tick TsunamiPChip::read(Packet *pkt) { - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); pkt->time += pioDelay; pkt->allocate(); - Addr daddr = (pkt->addr - pioAddr) >> 6;; - assert(pkt->size == sizeof(uint64_t)); + Addr daddr = (pkt->getAddr() - pioAddr) >> 6;; + assert(pkt->getSize() == sizeof(uint64_t)); - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->addr, pkt->size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); switch(daddr) { case TSDEV_PC_WSBA0: @@ -143,7 +143,7 @@ TsunamiPChip::read(Packet *pkt) default: panic("Default in PChip Read reached reading 0x%x\n", daddr); } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -153,13 +153,13 @@ TsunamiPChip::write(Packet *pkt) { pkt->time += pioDelay; - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - Addr daddr = (pkt->addr - pioAddr) >> 6; + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); + Addr daddr = (pkt->getAddr() - pioAddr) >> 6; - assert(pkt->size == sizeof(uint64_t)); + assert(pkt->getSize() == sizeof(uint64_t)); - DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->addr, pkt->size); + DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); switch(daddr) { case TSDEV_PC_WSBA0: @@ -224,7 +224,7 @@ TsunamiPChip::write(Packet *pkt) } // uint64_t - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc index a4b30cf25..8e6843841 100644 --- a/src/dev/uart8250.cc +++ b/src/dev/uart8250.cc @@ -110,12 +110,12 @@ Uart8250::Uart8250(Params *p) Tick Uart8250::read(Packet *pkt) { - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - assert(pkt->size == 1); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); + assert(pkt->getSize() == 1); pkt->time += pioDelay; - Addr daddr = pkt->addr - pioAddr; + Addr daddr = pkt->getAddr() - pioAddr; pkt->allocate(); DPRINTF(Uart, " read register %#x\n", daddr); @@ -186,7 +186,7 @@ Uart8250::read(Packet *pkt) /* uint32_t d32 = *data; DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32); */ - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } @@ -194,12 +194,12 @@ Tick Uart8250::write(Packet *pkt) { - assert(pkt->result == Unknown); - assert(pkt->addr >= pioAddr && pkt->addr < pioAddr + pioSize); - assert(pkt->size == 1); + assert(pkt->result == Packet::Unknown); + assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); + assert(pkt->getSize() == 1); pkt->time += pioDelay; - Addr daddr = pkt->addr - pioAddr; + Addr daddr = pkt->getAddr() - pioAddr; DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get()); @@ -264,7 +264,7 @@ Uart8250::write(Packet *pkt) panic("Tried to access a UART port that doesn't exist\n"); break; } - pkt->result = Success; + pkt->result = Packet::Success; return pioDelay; } -- cgit v1.2.3