From cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 22 Apr 2019 19:45:10 -0700 Subject: mem: Minimize the use of MemObject. MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro Reviewed-by: Anthony Gutierrez Maintainer: Gabe Black --- src/doc/memory_system.doxygen | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/doc/memory_system.doxygen') diff --git a/src/doc/memory_system.doxygen b/src/doc/memory_system.doxygen index 061a289ee..4fe982068 100644 --- a/src/doc/memory_system.doxygen +++ b/src/doc/memory_system.doxygen @@ -51,13 +51,13 @@ configs/example/fs.py --caches --cpu-type=arm_detailed --num-cpus=2 - Gem5 uses Memory Objects (MemObject) derived objects as basic blocks for + Gem5 uses Simulation Objects (SimObject) derived objects as basic blocks for building memory system. They are connected via ports with established master/slave hierarchy. Data flow is initiated on master port while the response messages and snoop queries appear on the slave port. The following - figure shows the hierarchy of Memory Objects used in this document: + figure shows the hierarchy of Simulation Objects used in this document: - \image html "gem5_MS_Fig1.PNG" "Memory Object hierarchy of the model" width=3cm + \image html "gem5_MS_Fig1.PNG" "Simulation Object hierarchy of the model" width=3cm \section gem5_CPU CPU @@ -77,7 +77,7 @@ Load & store buffers (for read and write access) don’t impose any restriction on the number of active memory accesses. Therefore, the maximum number of outstanding CPU’s memory access requests is not limited by CPU - Memory Object but by underlying memory system model. + Simulation Object but by underlying memory system model. Split memory access is implemented. @@ -89,7 +89,7 @@ Data Cache object implements a standard cache structure: - \image html "gem5_MS_Fig2.PNG" "DCache Memory Object" width=3cm + \image html "gem5_MS_Fig2.PNG" "DCache Simulation Object" width=3cm Cached memory reads that match particular cache tag (with Valid & Read flags) will be completed (by sending ReadResp to CPU) after a configurable time. -- cgit v1.2.3