From cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 22 Apr 2019 19:45:10 -0700 Subject: mem: Minimize the use of MemObject. MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro Reviewed-by: Anthony Gutierrez Maintainer: Gabe Black --- src/gpu-compute/X86GPUTLB.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/gpu-compute/X86GPUTLB.py') diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py index 963e2d147..a0ac9e9e6 100644 --- a/src/gpu-compute/X86GPUTLB.py +++ b/src/gpu-compute/X86GPUTLB.py @@ -35,16 +35,17 @@ from m5.defines import buildEnv from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject +from m5.SimObject import SimObject if buildEnv['FULL_SYSTEM']: - class X86PagetableWalker(MemObject): + class X86PagetableWalker(SimObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' port = SlavePort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") -class X86GPUTLB(MemObject): +class X86GPUTLB(ClockedObject): type = 'X86GPUTLB' cxx_class = 'X86ISA::GpuTLB' cxx_header = 'gpu-compute/gpu_tlb.hh' @@ -64,7 +65,7 @@ class X86GPUTLB(MemObject): allocationPolicy = Param.Bool(True, "Allocate on an access") accessDistance = Param.Bool(False, "print accessDistance stats") -class TLBCoalescer(MemObject): +class TLBCoalescer(ClockedObject): type = 'TLBCoalescer' cxx_class = 'TLBCoalescer' cxx_header = 'gpu-compute/tlb_coalescer.hh' -- cgit v1.2.3