From cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 13 Oct 2018 00:54:32 -0700 Subject: cpu: dev: sim: gpu-compute: Banish some ISA specific register types. These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are some remaining types, specifically the vector registers and the CCReg. I'm less familiar with these new types of registers, and so will look at getting rid of them at some later time. Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b Reviewed-on: https://gem5-review.googlesource.com/c/13624 Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/gpu-compute/gpu_exec_context.cc | 4 ++-- src/gpu-compute/gpu_exec_context.hh | 5 +++-- src/gpu-compute/gpu_tlb.cc | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) (limited to 'src/gpu-compute') diff --git a/src/gpu-compute/gpu_exec_context.cc b/src/gpu-compute/gpu_exec_context.cc index 013239757..76854f358 100644 --- a/src/gpu-compute/gpu_exec_context.cc +++ b/src/gpu-compute/gpu_exec_context.cc @@ -53,7 +53,7 @@ GPUExecContext::wavefront() return wf; } -TheGpuISA::MiscReg +RegVal GPUExecContext::readMiscReg(int opIdx) const { assert(gpuISA); @@ -61,7 +61,7 @@ GPUExecContext::readMiscReg(int opIdx) const } void -GPUExecContext::writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal) +GPUExecContext::writeMiscReg(int opIdx, RegVal operandVal) { assert(gpuISA); gpuISA->writeMiscReg(opIdx, operandVal); diff --git a/src/gpu-compute/gpu_exec_context.hh b/src/gpu-compute/gpu_exec_context.hh index c5f9929b9..4f67dba47 100644 --- a/src/gpu-compute/gpu_exec_context.hh +++ b/src/gpu-compute/gpu_exec_context.hh @@ -37,6 +37,7 @@ #define __GPU_EXEC_CONTEXT_HH__ #include "arch/gpu_isa.hh" +#include "base/types.hh" #include "config/the_gpu_isa.hh" class ComputeUnit; @@ -49,8 +50,8 @@ class GPUExecContext Wavefront* wavefront(); ComputeUnit* computeUnit(); - TheGpuISA::MiscReg readMiscReg(int opIdx) const; - void writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal); + RegVal readMiscReg(int opIdx) const; + void writeMiscReg(int opIdx, RegVal operandVal); protected: ComputeUnit *cu; diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc index dbf7d2628..9e07b0547 100644 --- a/src/gpu-compute/gpu_tlb.cc +++ b/src/gpu-compute/gpu_tlb.cc @@ -617,7 +617,7 @@ namespace X86ISA //The index is multiplied by the size of a MiscReg so that //any memory dependence calculations will not see these as //overlapping. - req->setPaddr(regNum * sizeof(MiscReg)); + req->setPaddr(regNum * sizeof(RegVal)); return NoFault; } else if (prefix == IntAddrPrefixIO) { // TODO If CPL > IOPL or in virtual mode, check the I/O permission @@ -630,7 +630,7 @@ namespace X86ISA if (IOPort == 0xCF8 && req->getSize() == 4) { req->setFlags(Request::MMAPPED_IPR); - req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); + req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal)); } else if ((IOPort & ~mask(2)) == 0xCFC) { req->setFlags(Request::UNCACHEABLE); -- cgit v1.2.3