From d3d24835bcc03ecf312ac6ba7df114656770730f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 7 Mar 2019 03:02:35 -0800 Subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort. Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/learning_gem5/part2/simple_cache.cc | 18 ++++-------------- src/learning_gem5/part2/simple_cache.hh | 21 ++++----------------- src/learning_gem5/part2/simple_memobj.cc | 20 ++++---------------- src/learning_gem5/part2/simple_memobj.hh | 21 ++++----------------- 4 files changed, 16 insertions(+), 64 deletions(-) (limited to 'src/learning_gem5') diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc index 1ddb5155e..880dc39ad 100644 --- a/src/learning_gem5/part2/simple_cache.cc +++ b/src/learning_gem5/part2/simple_cache.cc @@ -51,30 +51,20 @@ SimpleCache::SimpleCache(SimpleCacheParams *params) : } } -BaseMasterPort& -SimpleCache::getMasterPort(const std::string& if_name, PortID idx) +Port & +SimpleCache::getPort(const std::string &if_name, PortID idx) { panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); // This is the name from the Python SimObject declaration in SimpleCache.py if (if_name == "mem_side") { return memPort; - } else { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -SimpleCache::getSlavePort(const std::string& if_name, PortID idx) -{ - // This is the name from the Python SimObject declaration (SimpleMemobj.py) - if (if_name == "cpu_side" && idx < cpuPorts.size()) { + } else if (if_name == "cpu_side" && idx < cpuPorts.size()) { // We should have already created all of the ports in the constructor return cpuPorts[idx]; } else { // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/learning_gem5/part2/simple_cache.hh b/src/learning_gem5/part2/simple_cache.hh index 7d53ffed0..56859eb77 100644 --- a/src/learning_gem5/part2/simple_cache.hh +++ b/src/learning_gem5/part2/simple_cache.hh @@ -304,30 +304,17 @@ class SimpleCache : public MemObject SimpleCache(SimpleCacheParams *params); /** - * Get a master port with a given name and index. This is used at + * Get a port with a given name and index. This is used at * binding time and returns a reference to a protocol-agnostic - * base master port. + * port. * * @param if_name Port name * @param idx Index in the case of a VectorPort * * @return A reference to the given port */ - virtual BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) override; - - /** - * Get a slave port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - virtual BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * Register the stats diff --git a/src/learning_gem5/part2/simple_memobj.cc b/src/learning_gem5/part2/simple_memobj.cc index cb4d3d8db..c9af3461f 100644 --- a/src/learning_gem5/part2/simple_memobj.cc +++ b/src/learning_gem5/part2/simple_memobj.cc @@ -41,33 +41,21 @@ SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) : { } -BaseMasterPort& -SimpleMemobj::getMasterPort(const std::string& if_name, PortID idx) +Port & +SimpleMemobj::getPort(const std::string &if_name, PortID idx) { panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); // This is the name from the Python SimObject declaration (SimpleMemobj.py) if (if_name == "mem_side") { return memPort; - } else { - // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); - } -} - -BaseSlavePort& -SimpleMemobj::getSlavePort(const std::string& if_name, PortID idx) -{ - panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); - - // This is the name from the Python SimObject declaration in SimpleCache.py - if (if_name == "inst_port") { + } else if (if_name == "inst_port") { return instPort; } else if (if_name == "data_port") { return dataPort; } else { // pass it along to our super class - return MemObject::getSlavePort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/learning_gem5/part2/simple_memobj.hh b/src/learning_gem5/part2/simple_memobj.hh index a44d4336c..7a9b44764 100644 --- a/src/learning_gem5/part2/simple_memobj.hh +++ b/src/learning_gem5/part2/simple_memobj.hh @@ -235,30 +235,17 @@ class SimpleMemobj : public MemObject SimpleMemobj(SimpleMemobjParams *params); /** - * Get a master port with a given name and index. This is used at + * Get a port with a given name and index. This is used at * binding time and returns a reference to a protocol-agnostic - * base master port. + * port. * * @param if_name Port name * @param idx Index in the case of a VectorPort * * @return A reference to the given port */ - BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) override; - - /** - * Get a slave port with a given name and index. This is used at - * binding time and returns a reference to a protocol-agnostic - * base master port. - * - * @param if_name Port name - * @param idx Index in the case of a VectorPort - * - * @return A reference to the given port - */ - BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; }; -- cgit v1.2.3