From 0f33b2c1d5875aae036a9e2779f6e9c764e0f85e Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 2 May 2018 13:55:10 +0100 Subject: mem: Add a memory delay simulator Add a memory system component that delays traffic. The base functionality to delay packets is implemented in the abstract MemDelay class. This class exposes three methods that control packet delays: * delayReq(pkt) * delayResp(pkt) * delaySnoopResp(pkt) These methods should be specialized to implement delays for specific packet types. The class SimpleMemDelay uses the MemDelay base class to implement constant delays for read/write requests and responses. The intention is that these classes can be used for rapid prototyping of components that add a small fixed delay and the same throughput as the interconnect. I.e., any buffering done in the base class will be small and proportional to the introduced delay. Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628 Signed-off-by: Andreas Sandberg Reviewed-by: Nicholas Lindsey Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/11521 Reviewed-by: Daniel Carvalho Reviewed-by: Jason Lowe-Power Maintainer: Nikos Nikoleris --- src/mem/SConscript | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mem/SConscript') diff --git a/src/mem/SConscript b/src/mem/SConscript index 625eb0608..7c0d426d7 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -44,6 +44,7 @@ SimObject('SimpleMemory.py') SimObject('XBar.py') SimObject('HMCController.py') SimObject('SerialLink.py') +SimObject('MemDelay.py') Source('abstract_mem.cc') Source('addr_mapper.cc') @@ -68,6 +69,7 @@ Source('tport.cc') Source('xbar.cc') Source('hmc_controller.cc') Source('serial_link.cc') +Source('mem_delay.cc') if env['TARGET_ISA'] != 'null': Source('fs_translating_port_proxy.cc') -- cgit v1.2.3