From 1530e1a690a7d3c1b028e59d2fa37c88df8e47df Mon Sep 17 00:00:00 2001 From: Erfan Azarkhish Date: Tue, 3 Nov 2015 12:17:56 -0600 Subject: mem: hmc: adds controller This patch models a simple HMC Controller. It simply schedules the incoming packets to HMC Serial Links using a round robin mechanism. This patch should be applied in series with other patches modeling a complete HMC device. Committed by: Nilay Vaish --- src/mem/SConscript | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mem/SConscript') diff --git a/src/mem/SConscript b/src/mem/SConscript index 404f4a90f..3b65131a2 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -42,6 +42,7 @@ SimObject('ExternalSlave.py') SimObject('MemObject.py') SimObject('SimpleMemory.py') SimObject('XBar.py') +SimObject('HMCController.py') Source('abstract_mem.cc') Source('addr_mapper.cc') @@ -64,6 +65,7 @@ Source('snoop_filter.cc') Source('stack_dist_calc.cc') Source('tport.cc') Source('xbar.cc') +Source('hmc_controller.cc') if env['TARGET_ISA'] != 'null': Source('fs_translating_port_proxy.cc') @@ -101,6 +103,7 @@ DebugFlag('MemoryAccess') DebugFlag('PacketQueue') DebugFlag('StackDist') DebugFlag("DRAMSim2") +DebugFlag('HMCController') DebugFlag("MemChecker") DebugFlag("MemCheckerMonitor") -- cgit v1.2.3