From 1f6d5f8f849f50a3646f586b1274708537124ef3 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Sat, 20 Sep 2014 17:18:32 -0400
Subject: mem: Rename Bus to XBar to better reflect its behaviour

This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.

As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.

--HG--
rename : src/mem/Bus.py => src/mem/XBar.py
rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc
rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh
rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc
rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh
rename : src/mem/bus.cc => src/mem/xbar.cc
rename : src/mem/bus.hh => src/mem/xbar.hh
---
 src/mem/SConscript | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

(limited to 'src/mem/SConscript')

diff --git a/src/mem/SConscript b/src/mem/SConscript
index c351661b8..35f2e9ce4 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -39,28 +39,28 @@ if env['HAVE_PROTOBUF']:
 SimObject('AbstractMemory.py')
 SimObject('AddrMapper.py')
 SimObject('Bridge.py')
-SimObject('Bus.py')
 SimObject('DRAMCtrl.py')
 SimObject('MemObject.py')
 SimObject('SimpleMemory.py')
+SimObject('XBar.py')
 
 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
 Source('bridge.cc')
-Source('bus.cc')
-Source('coherent_bus.cc')
+Source('coherent_xbar.cc')
 Source('dram_ctrl.cc')
 Source('mem_object.cc')
 Source('mport.cc')
-Source('noncoherent_bus.cc')
+Source('noncoherent_xbar.cc')
 Source('packet.cc')
 Source('port.cc')
 Source('packet_queue.cc')
-Source('tport.cc')
 Source('port_proxy.cc')
-Source('simple_mem.cc')
 Source('physical.cc')
+Source('simple_mem.cc')
 Source('snoop_filter.cc')
+Source('tport.cc')
+Source('xbar.cc')
 
 if env['TARGET_ISA'] != 'null':
     Source('fs_translating_port_proxy.cc')
@@ -74,13 +74,13 @@ if env['HAVE_DRAMSIM']:
     Source('dramsim2_wrapper.cc')
     Source('dramsim2.cc')
 
-DebugFlag('BaseBus')
-DebugFlag('BusAddrRanges')
-DebugFlag('CoherentBus')
-DebugFlag('NoncoherentBus')
+DebugFlag('AddrRanges')
+DebugFlag('BaseXBar')
+DebugFlag('CoherentXBar')
+DebugFlag('NoncoherentXBar')
 DebugFlag('SnoopFilter')
-CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
-                     'NoncoherentBus', 'SnoopFilter'])
+CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
+                      'SnoopFilter'])
 
 DebugFlag('Bridge')
 DebugFlag('CommMonitor')
-- 
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