From 3b6a143ec577b74a3bc65b84d3fe0416a094b2d0 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 21 Sep 2012 11:48:13 -0400 Subject: DRAM: Introduce SimpleDRAM to capture a high-level controller This patch introduces a high-level model of a DRAM controller, with a basic read/write buffer structure, a selectable and customisable arbiter, a few address mapping options, and the basic DRAM timing constraints. The parameters make it possible to turn this model into any desired DDRx/LPDDRx/WideIOx memory controller. The intention is not to be cycle accurate or capture every aspect of a DDR DRAM interface, but rather to enable exploring of the high-level knobs with a good simulation speed. Thus, contrary to e.g. DRAMSim this module emphasizes simulation speed with a good-enough accuracy. This module is merely a starting point, and there are plenty additions and improvements to come. A notable addition is the support for address-striping in the bus to enable a multi-channel DRAM controller. Also note that there are still a few "todo's" in the code base that will be addressed as we go along. A follow-up patch will add basic performance regressions that use the traffic generator to exercise a few well-defined corner cases. --- src/mem/SConscript | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mem/SConscript') diff --git a/src/mem/SConscript b/src/mem/SConscript index 7aba4f0e7..1c43975df 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -53,10 +53,12 @@ Source('se_translating_port_proxy.cc') if env['TARGET_ISA'] != 'no': SimObject('AbstractMemory.py') SimObject('SimpleMemory.py') + SimObject('SimpleDRAM.py') Source('abstract_mem.cc') Source('simple_mem.cc') Source('page_table.cc') Source('physical.cc') + Source('simple_dram.cc') DebugFlag('BaseBus') DebugFlag('BusAddrRanges') @@ -67,6 +69,8 @@ CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', DebugFlag('Bridge') DebugFlag('CommMonitor') +DebugFlag('DRAM') +DebugFlag('DRAMWR') DebugFlag('LLSC') DebugFlag('MMU') DebugFlag('MemoryAccess') -- cgit v1.2.3