From 93f2f69657d0a2420a2c86b71505e6d27e6e2a38 Mon Sep 17 00:00:00 2001 From: Daniel Sanchez Date: Mon, 11 May 2009 10:38:46 -0700 Subject: ruby: Working M5 interface and updated Ruby interface. This changeset also includes a lot of work from Derek Hower RubyMemory is now both a driver for Ruby and a port for M5. Changed makeRequest/hitCallback interface. Brought packets (superficially) into the sequencer. Modified tester infrastructure to be packet based. and Ruby can be used together through the example ruby_se.py script. SPARC parallel applications work, and the timing *seems* right from combined M5/Ruby debug traces. To run, % build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t --- src/mem/SConscript | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mem/SConscript') diff --git a/src/mem/SConscript b/src/mem/SConscript index 0b0017f81..87498d21d 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -32,8 +32,9 @@ Import('*') SimObject('Bridge.py') SimObject('Bus.py') -SimObject('PhysicalMemory.py') SimObject('MemObject.py') +SimObject('PhysicalMemory.py') +SimObject('RubyMemory.py') Source('bridge.cc') Source('bus.cc') @@ -44,6 +45,7 @@ Source('physical.cc') Source('port.cc') Source('tport.cc') Source('mport.cc') +Source('rubymem.cc') if env['FULL_SYSTEM']: Source('vport.cc') -- cgit v1.2.3 From cf6b4ef734293e1efdfa015519230703be5d324a Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 11 May 2009 10:38:46 -0700 Subject: ruby: add RUBY sticky option that must be set to add ruby to the build Default is false --- src/mem/SConscript | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mem/SConscript') diff --git a/src/mem/SConscript b/src/mem/SConscript index 87498d21d..21335a709 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -34,7 +34,9 @@ SimObject('Bridge.py') SimObject('Bus.py') SimObject('MemObject.py') SimObject('PhysicalMemory.py') -SimObject('RubyMemory.py') + +if env['RUBY']: + SimObject('RubyMemory.py') Source('bridge.cc') Source('bus.cc') @@ -45,7 +47,9 @@ Source('physical.cc') Source('port.cc') Source('tport.cc') Source('mport.cc') -Source('rubymem.cc') + +if env['RUBY']: + Source('rubymem.cc') if env['FULL_SYSTEM']: Source('vport.cc') -- cgit v1.2.3