From d6732895a5c2e81da47ada339b5d9269c02e5e8b Mon Sep 17 00:00:00 2001 From: Andrew Bardsley Date: Thu, 16 Oct 2014 05:49:56 -0400 Subject: mem: Add ExternalMaster and ExternalSlave ports This patch adds two MemoryObject's: ExternalMaster and ExternalSlave. Each object has a single port which can be bound to an externally- provided bridge to a port of another simulation system at initialisation. --- src/mem/SConscript | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mem/SConscript') diff --git a/src/mem/SConscript b/src/mem/SConscript index 6d225385b..e7d2c1bac 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -40,6 +40,8 @@ SimObject('AbstractMemory.py') SimObject('AddrMapper.py') SimObject('Bridge.py') SimObject('DRAMCtrl.py') +SimObject('ExternalMaster.py') +SimObject('ExternalSlave.py') SimObject('MemObject.py') SimObject('SimpleMemory.py') SimObject('XBar.py') @@ -50,6 +52,8 @@ Source('bridge.cc') Source('coherent_xbar.cc') Source('drampower.cc') Source('dram_ctrl.cc') +Source('external_master.cc') +Source('external_slave.cc') Source('mem_object.cc') Source('mport.cc') Source('noncoherent_xbar.cc') @@ -88,6 +92,7 @@ DebugFlag('CommMonitor') DebugFlag('DRAM') DebugFlag('DRAMPower') DebugFlag('DRAMState') +DebugFlag('ExternalPort') DebugFlag('LLSC') DebugFlag('MMU') DebugFlag('MemoryAccess') -- cgit v1.2.3