From 3ba131f4d50e17170531ea69bd1d3733f498e381 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 1 Mar 2013 13:20:22 -0500 Subject: mem: Add support for multi-channel DRAM configurations This patch adds support for multi-channel instances of the DRAM controller model by stripping away the channel bits in the address decoding. The patch relies on the availiability of address interleaving and, at this time, it is up to the user to configure the interleaving appropriately. At the moment it is assumed that the channel interleaving bits are immediately following the column bits (smallest sensible interleaving). Convenience methods for building multi-channel configurations will be added later. --- src/mem/SimpleDRAM.py | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mem/SimpleDRAM.py') diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index 41bad9356..0e43a6a39 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -80,6 +80,10 @@ class SimpleDRAM(AbstractMemory): lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") ranks_per_channel = Param.Unsigned("Number of ranks per channel") banks_per_rank = Param.Unsigned("Number of banks per rank") + # only used for the address mapping as the controller by + # construction is a single channel and multiple controllers have + # to be instantiated for a multi-channel configuration + channels = Param.Unsigned(1, "Number of channels") # timing behaviour and constraints - all in nanoseconds -- cgit v1.2.3