From d82bffd2979ea9dec286dca1b2d10cadc111293a Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 30 May 2013 12:54:12 -0400 Subject: mem: Add static latency to the DRAM controller This patch adds a frontend and backend static latency to the DRAM controller by delaying the responses. Two parameters expressing the frontend and backend contributions in absolute time are added to the controller, and the appropriate latency is added to the responses when adding them to the (infinite) queued port for sending. For writes and reads that hit in the write buffer, only the frontend latency is added. For reads that are serviced by the DRAM, the static latency is the sum of the pipeline latencies of the entire frontend, backend and PHY. The default values are chosen based on having roughly 10 pipeline stages in total at 500 MHz. In the future, it would be sensible to make the controller use its clock and convert these latencies (and a few of the DRAM timings) to cycles. --- src/mem/SimpleDRAM.py | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mem/SimpleDRAM.py') diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index 9101de101..75c5b077b 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -110,6 +110,13 @@ class SimpleDRAM(AbstractMemory): addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") page_policy = Param.PageManage('open', "Page closure management policy") + # pipeline latency of the controller and PHY, split into a + # frontend part and a backend part, with reads and writes serviced + # by the queues only seeing the frontend contribution, and reads + # serviced by the memory seeing the sum of the two + static_frontend_latency = Param.Latency("10ns", "Static frontend latency") + static_backend_latency = Param.Latency("10ns", "Static backend latency") + # the physical organisation of the DRAM lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") ranks_per_channel = Param.Unsigned("Number of ranks per channel") -- cgit v1.2.3