From 7c55464aac2bcab15699e563f18a7d3d565d949a Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 18 Sep 2012 10:30:02 -0400 Subject: Mem: Add a maximum bandwidth to SimpleMemory This patch makes a minor addition to the SimpleMemory by enforcing a maximum data rate. The bandwidth is configurable, and a reasonable value (12.8GB/s) has been choosen as the default. The changes do add some complexity to the SimpleMemory, but they should definitely be justifiable as this enables a far more realistic setup using even this simple memory controller. The rate regulation is done for reads and writes combined to reflect the bidirectional data busses used by most (if not all) relevant memories. Moreover, the regulation is done per packet as opposed to long term, as it is the short term data rate (data bus width times frequency) that is the limiting factor. A follow-up patch bumps the stats for the regressions. --- src/mem/SimpleMemory.py | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mem/SimpleMemory.py') diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index c47d04222..9361b45d8 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -47,3 +47,7 @@ class SimpleMemory(AbstractMemory): port = SlavePort("Slave ports") latency = Param.Latency('30ns', "Request to response latency") latency_var = Param.Latency('0ns', "Request to response latency variance") + # The memory bandwidth limit default is set to 12.8GB/s which is + # representative of a x64 DDR3-1600 channel. + bandwidth = Param.MemoryBandwidth('12.8GB/s', + "Combined read and write bandwidth") -- cgit v1.2.3