From f00cba34eb8e6bf947721f72de314f4e8bd6a8f8 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 12 Jul 2012 12:56:13 -0400 Subject: Mem: Make SimpleMemory single ported This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses. --- src/mem/SimpleMemory.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mem/SimpleMemory.py') diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index 51de3374d..c47d04222 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -44,6 +44,6 @@ from AbstractMemory import * class SimpleMemory(AbstractMemory): type = 'SimpleMemory' - port = VectorSlavePort("Slave ports") + port = SlavePort("Slave ports") latency = Param.Latency('30ns', "Request to response latency") latency_var = Param.Latency('0ns', "Request to response latency variance") -- cgit v1.2.3