From 1f6d5f8f849f50a3646f586b1274708537124ef3 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Sat, 20 Sep 2014 17:18:32 -0400 Subject: mem: Rename Bus to XBar to better reflect its behaviour This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh --- src/mem/bridge.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mem/bridge.cc') diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index 3b101ceab..085c97b53 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -44,7 +44,7 @@ /** * @file - * Implementation of a memory-mapped bus bridge that connects a master + * Implementation of a memory-mapped bridge that connects a master * and a slave through a request and response queue. */ @@ -108,7 +108,7 @@ Bridge::init() { // make sure both sides are connected and have the same block size if (!slavePort.isConnected() || !masterPort.isConnected()) - fatal("Both ports of bus bridge are not connected to a bus.\n"); + fatal("Both ports of a bridge must be connected.\n"); // notify the master side of our address ranges slavePort.sendRangeChange(); @@ -137,7 +137,7 @@ Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt) DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size()); // @todo: We need to pay for this and not just zero it out - pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + pkt->firstWordDelay = pkt->lastWordDelay = 0; slavePort.schedTimingResp(pkt, bridge.clockEdge(delay)); @@ -181,7 +181,7 @@ Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt) if (!retryReq) { // @todo: We need to pay for this and not just zero it out - pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; + pkt->firstWordDelay = pkt->lastWordDelay = 0; masterPort.schedTimingReq(pkt, bridge.clockEdge(delay)); } @@ -209,7 +209,7 @@ Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when) { // If we expect to see a response, we need to restore the source // and destination field that is potentially changed by a second - // bus + // crossbar if (!pkt->memInhibitAsserted() && pkt->needsResponse()) { // Update the sender state so we can deal with the response // appropriately @@ -242,7 +242,7 @@ Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when) pkt->setDest(req_state->origSrc); delete req_state; - // the bridge assumes that at least one bus has set the + // the bridge assumes that at least one crossbar has set the // destination field of the packet assert(pkt->isDestValid()); DPRINTF(Bridge, "response, new dest %d\n", pkt->getDest()); -- cgit v1.2.3