From 06a9f58c68b621f082d39299bdb01f59ef68ef0e Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Fri, 10 Aug 2007 16:14:01 -0400
Subject: DMA: Add IOCache and fix bus bridge to optionally only send requests
 one way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
---
 src/mem/bus.cc | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/mem/bus.cc')

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index eba96b4d2..42c4431bb 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -457,6 +457,10 @@ Bus::recvStatusChange(Port::Status status, int id)
     bool snoops;
     AddrRangeIter iter;
 
+    if (inRecvStatusChange.count(id))
+        return;
+    inRecvStatusChange.insert(id);
+
     assert(status == Port::RangeChange &&
            "The other statuses need to be implemented.");
 
@@ -524,6 +528,7 @@ Bus::recvStatusChange(Port::Status status, int id)
 
     if (id != defaultId && defaultPort)
         defaultPort->sendStatusChange(Port::RangeChange);
+    inRecvStatusChange.erase(id);
 }
 
 void
-- 
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