From b3fc8839c4727da575ed916cbd6a76d8ad5fc644 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 19 Feb 2013 05:56:06 -0500 Subject: mem: Make packet bus-related time accounting relative This patch changes the bus-related time accounting done in the packet to be relative. Besides making it easier to align the cache timing to cache clock cycles, it also makes it possible to create a Last-Level Cache (LLC) directly to a memory controller without a bus inbetween. The bus is unique in that it does not ever make the packets wait to reflect the time spent forwarding them. Instead, the cache is currently responsible for making the packets wait. Thus, the bus annotates the packets with the time needed for the first word to appear, and also the last word. The cache then delays the packets in its queues before passing them on. It is worth noting that every object attached to a bus (devices, memories, bridges, etc) should be doing this if we opt for keeping this way of accounting for the bus timing. --- src/mem/bus.cc | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) (limited to 'src/mem/bus.cc') diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 4d9cdbe88..690d85373 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -129,30 +129,24 @@ BaseBus::getSlavePort(const std::string &if_name, PortID idx) } } -Tick +void BaseBus::calcPacketTiming(PacketPtr pkt) { - // determine the header time rounded to the closest following - // clock edge - Tick headerTime = clockEdge(headerCycles); - - // The packet will be sent. Figure out how long it occupies the bus, and - // how much of that time is for the first "word", aka bus width. - Cycles numCycles(0); - if (pkt->hasData()) { - // If a packet has data, it needs ceil(size/width) cycles to send it - unsigned dataSize = pkt->getSize(); - numCycles = Cycles(divCeil(dataSize, width)); - } + // the bus will be called at a time that is not necessarily + // coinciding with its own clock, so start by determining how long + // until the next clock edge (could be zero) + Tick offset = nextCycle() - curTick(); - // The first word will be delivered on the cycle after the header. - pkt->firstWordTime = headerTime + clockPeriod(); + // determine how many cycles are needed to send the data + unsigned dataCycles = pkt->hasData() ? divCeil(pkt->getSize(), width) : 0; - // Note that currently finishTime can be smaller than - // firstWordTime if the packet has no data - pkt->finishTime = headerTime + numCycles * clockPeriod(); + // The first word will be delivered on the cycle after the header. + pkt->busFirstWordDelay = (headerCycles + 1) * clockPeriod() + offset; - return headerTime; + // Note that currently busLastWordDelay can be smaller than + // busFirstWordDelay if the packet has no data + pkt->busLastWordDelay = (headerCycles + dataCycles) * clockPeriod() + + offset; } template -- cgit v1.2.3