From d9172c8f462511cde474040581063180be18540a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 5 Oct 2006 16:26:16 -0400 Subject: Partial reimplementation of the bus. The "clock" and "width" parameters have been added, and the HasData flag has been partially added to packets. --HG-- extra : convert_revision : abb2a259fcf843457abbc0bd36f9504fbe6d7d39 --- src/mem/bus.hh | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'src/mem/bus.hh') diff --git a/src/mem/bus.hh b/src/mem/bus.hh index 941389296..9dd666304 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -51,6 +51,14 @@ class Bus : public MemObject { /** a globally unique id for this bus. */ int busId; + /** the clock speed for the bus */ + int clock; + /** the width of the bus in bits */ + int width; + /** the last tick the address bus was used */ + Tick tickAddrLastUsed; + /** the last tick the data bus was used */ + Tick tickDataLastUsed; static const int defaultId = -1; @@ -199,8 +207,12 @@ class Bus : public MemObject virtual void init(); - Bus(const std::string &n, int bus_id) - : MemObject(n), busId(bus_id), defaultPort(NULL) {} + Bus(const std::string &n, int bus_id, int _clock, int _width) + : MemObject(n), busId(bus_id), clock(_clock), width(_width), + tickAddrLastUsed(0), tickDataLastUsed(0), defaultPort(NULL) + { + assert(width); + } }; -- cgit v1.2.3 From 00481d1f192c832d654379c2296d5b6020c12b1a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 8 Oct 2006 14:08:58 -0400 Subject: A possible implementation of a multiplexed bus. --HG-- extra : convert_revision : 3c560eda12ffd8ca539c91024baf2770b963ede8 --- src/mem/bus.hh | 53 ++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 5 deletions(-) (limited to 'src/mem/bus.hh') diff --git a/src/mem/bus.hh b/src/mem/bus.hh index 9dd666304..96f1152a6 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -46,6 +46,7 @@ #include "mem/packet.hh" #include "mem/port.hh" #include "mem/request.hh" +#include "sim/eventq.hh" class Bus : public MemObject { @@ -55,10 +56,8 @@ class Bus : public MemObject int clock; /** the width of the bus in bits */ int width; - /** the last tick the address bus was used */ - Tick tickAddrLastUsed; - /** the last tick the data bus was used */ - Tick tickDataLastUsed; + /** the next tick at which the bus will be idle */ + Tick tickNextIdle; static const int defaultId = -1; @@ -101,6 +100,15 @@ class Bus : public MemObject */ Port *findPort(Addr addr, int id); + /** Finds the port a packet should be sent to. If the bus is blocked, no port + * is returned. + * @param pkt Packet to find a destination port for. + * @param id Id of the port this packet was received from + * (to prevent loops) + */ + + Port *findDestPort(PacketPtr pkt, int id); + /** Find all ports with a matching snoop range, except src port. Keep in mind * that the ranges shouldn't overlap or you will get a double snoop to the same * interface.and the cache will assert out. @@ -189,6 +197,22 @@ class Bus : public MemObject }; + class BusFreeEvent : public Event + { + Bus * bus; + + public: + BusFreeEvent(Bus * _bus); + void process(); + const char *description(); + }; + + BusFreeEvent busIdle; + + void occupyBus(int numCycles); + + Port * retryingPort; + /** An array of pointers to the peer port interfaces connected to this bus.*/ std::vector interfaces; @@ -197,6 +221,23 @@ class Bus : public MemObject * original send failed for whatever reason.*/ std::list retryList; + void addToRetryList(Port * port) + { + if (!retryingPort) { + // The device wasn't retrying a packet, or wasn't at an appropriate + // time. + retryList.push_back(port); + } else { + // The device was retrying a packet. It didn't work, so we'll leave + // it at the head of the retry list. + retryingPort = 0; + + // We shouldn't be receiving a packet from one port when a different + // one is retrying. + assert(port == retryingPort); + } + } + /** Port that handles requests that don't match any of the interfaces.*/ Port *defaultPort; @@ -209,9 +250,11 @@ class Bus : public MemObject Bus(const std::string &n, int bus_id, int _clock, int _width) : MemObject(n), busId(bus_id), clock(_clock), width(_width), - tickAddrLastUsed(0), tickDataLastUsed(0), defaultPort(NULL) + tickNextIdle(0), busIdle(this), retryingPort(0), defaultPort(NULL) { + //Both the width and clock period must be positive assert(width); + assert(clock); } }; -- cgit v1.2.3 From a82f017591ecb78cb098e38314d87d64fcaaa37f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 8 Oct 2006 18:44:49 -0400 Subject: bus changes src/mem/bus.cc: src/mem/bus.hh: minor fix and some formatting changes src/python/m5/objects/Bus.py: changed bits to bytes --HG-- extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5 --- src/mem/bus.hh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mem/bus.hh') diff --git a/src/mem/bus.hh b/src/mem/bus.hh index 96f1152a6..f238f134d 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -54,7 +54,7 @@ class Bus : public MemObject int busId; /** the clock speed for the bus */ int clock; - /** the width of the bus in bits */ + /** the width of the bus in bytes */ int width; /** the next tick at which the bus will be idle */ Tick tickNextIdle; @@ -230,7 +230,7 @@ class Bus : public MemObject } else { // The device was retrying a packet. It didn't work, so we'll leave // it at the head of the retry list. - retryingPort = 0; + retryingPort = NULL; // We shouldn't be receiving a packet from one port when a different // one is retrying. @@ -250,7 +250,7 @@ class Bus : public MemObject Bus(const std::string &n, int bus_id, int _clock, int _width) : MemObject(n), busId(bus_id), clock(_clock), width(_width), - tickNextIdle(0), busIdle(this), retryingPort(0), defaultPort(NULL) + tickNextIdle(0), busIdle(this), retryingPort(NULL), defaultPort(NULL) { //Both the width and clock period must be positive assert(width); -- cgit v1.2.3