From 427ceb57a9e1c7e226a549fda4556211bf206066 Mon Sep 17 00:00:00 2001 From: "Timothy M. Jones" Date: Fri, 24 Jan 2014 15:29:30 -0600 Subject: Cache: Collect very basic stats on tag and data accesses Adds very basic statistics on the number of tag and data accesses within the cache, which is important for power modelling. For the tags, simply count the associativity of the cache each time. For the data, this depends on whether tags and data are accessed sequentially, which is given by a new parameter. In the parallel case, all data blocks are accessed each time, but with sequential accesses, a single data block is accessed only on a hit. --- src/mem/cache/BaseCache.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mem/cache/BaseCache.py') diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index df4602199..9ffe39981 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -69,4 +69,6 @@ class BaseCache(MemObject): mem_side = MasterPort("Port on side closer to MEM") addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port") system = Param.System(Parent.any, "System we belong to") + sequential_access = Param.Bool(False, + "Whether to access tags and data sequentially") tags = Param.BaseTags(LRU(), "Tag Store for LRU caches") -- cgit v1.2.3