From 51056cec69a72931a319e7be9370ea63f18e1aa3 Mon Sep 17 00:00:00 2001 From: Nikos Nikoleris Date: Mon, 5 Feb 2018 09:45:20 +0000 Subject: mem-cache: Add a non-coherent cache The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris Reviewed-by: Daniel Carvalho --- src/mem/cache/SConscript | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mem/cache/SConscript') diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 1c9b0027c..244d61dc2 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -33,10 +33,11 @@ Import('*') SimObject('Cache.py') Source('base.cc') -Source('cache.cc') Source('blk.cc') +Source('cache.cc') Source('mshr.cc') Source('mshr_queue.cc') +Source('noncoherent_cache.cc') Source('write_queue.cc') Source('write_queue_entry.cc') -- cgit v1.2.3