From ccc50b7355fa9964c6da3ca1de2b3c48b7728bae Mon Sep 17 00:00:00 2001 From: Nikos Nikoleris Date: Tue, 27 Nov 2018 16:55:50 +0000 Subject: mem: Determine if a packet queue forces ordering at construction A packet queue is typically used to hold on to packets that are schedules to be sent in the future or when they need to queue behind younger packets that have been sent out yet. Due to memory order requirements, some MemObjects need to maintain the order for packet (mostly responses) that reference the same cache block. Prior to this patch the ordering requirements where determined when the packet was scheduled to be sent. This patch moves the parameter to the constructor. Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164 Signed-off-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/15555 Reviewed-by: Daniel Carvalho Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/mem/cache/base.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/mem/cache/base.cc') diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 08cd09fc5..6049ca6a6 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -69,7 +69,8 @@ using namespace std; BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, BaseCache *_cache, const std::string &_label) - : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), + : QueuedSlavePort(_name, _cache, queue), + queue(*_cache, *this, true, _label), blocked(false), mustSendRetry(false), sendRetryEvent([this]{ processSendRetry(); }, _name) { @@ -228,7 +229,7 @@ BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) // lat, neglecting responseLatency, modelling hit latency // just as the value of lat overriden by access(), which calls // the calculateAccessLatency() function. - cpuSidePort.schedTimingResp(pkt, request_time, true); + cpuSidePort.schedTimingResp(pkt, request_time); } else { DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, pkt->print()); @@ -400,7 +401,7 @@ BaseCache::handleUncacheableWriteResp(PacketPtr pkt) // Reset the bus additional time as it is now accounted for pkt->headerDelay = pkt->payloadDelay = 0; - cpuSidePort.schedTimingResp(pkt, completion_time, true); + cpuSidePort.schedTimingResp(pkt, completion_time); } void @@ -2400,7 +2401,7 @@ BaseCache::MemSidePort::MemSidePort(const std::string &_name, const std::string &_label) : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), _reqQueue(*_cache, *this, _snoopRespQueue, _label), - _snoopRespQueue(*_cache, *this, _label), cache(_cache) + _snoopRespQueue(*_cache, *this, true, _label), cache(_cache) { } -- cgit v1.2.3