From c6e0d8f54f1ce90933f95a7a3a875fed53b8ee3e Mon Sep 17 00:00:00 2001 From: "Daniel R. Carvalho" Date: Thu, 18 Oct 2018 15:31:51 +0200 Subject: mem-cache: Move access latency calculation to Cache Access latency was not being calculated properly, as it was always assuming that for hits reads take as long as writes, and that parallel accesses would produce the same latency for read and write misses. By moving the calculation to the Cache we can use the write/ read information, reduce latency variables duplication and remove Cache dependency from Tags. The tag lookup latency is still calculated by the Tags. Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540 Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/13697 Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- src/mem/cache/base.hh | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/mem/cache/base.hh') diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index ad5ff3bc4..240bf216f 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -418,6 +418,17 @@ class BaseCache : public MemObject */ Addr regenerateBlkAddr(CacheBlk* blk); + /** + * Calculate access latency in ticks given a tag lookup latency, and + * whether access was a hit or miss. + * + * @param blk The cache block that was accessed. + * @param lookup_lat Latency of the respective tag lookup. + * @return The number of ticks that pass due to a block access. + */ + Cycles calculateAccessLatency(const CacheBlk* blk, + const Cycles lookup_lat) const; + /** * Does all the processing necessary to perform the provided request. * @param pkt The memory request to perform. @@ -805,6 +816,11 @@ class BaseCache : public MemObject */ const Cycles responseLatency; + /** + * Whether tags and data are accessed sequentially. + */ + const bool sequentialAccess; + /** The number of targets for each MSHR. */ const int numTarget; -- cgit v1.2.3