From 6592045cbc138306474d24d60daa222a07673fe2 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 10 Jul 2006 17:16:15 -0400
Subject: Some fixes so that MSHR's are matched and we don't issue overlapping
 requests with detailed cpu

src/mem/cache/base_cache.cc:
    If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
    Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
    Actually save the address, otherwise we can't match MSHR's

--HG--
extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
---
 src/mem/cache/base_cache.cc | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

(limited to 'src/mem/cache/base_cache.cc')

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index be9769fdc..451da28e8 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -117,11 +117,24 @@ BaseCache::CacheEvent::process()
     if (!pkt)
     {
         if (!cachePort->isCpuSide)
+        {
             pkt = cachePort->cache->getPacket();
+            bool success = cachePort->sendTiming(pkt);
+            DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
+                    pkt->getAddr(), success ? "succesful" : "unsuccesful");
+            cachePort->cache->sendResult(pkt, success);
+            if (success && cachePort->cache->doMasterRequest())
+            {
+                //Still more to issue, rerequest in 1 cycle
+                pkt = NULL;
+                this->schedule(curTick+1);
+            }
+        }
         else
+        {
             pkt = cachePort->cache->getCoherencePacket();
-        bool success = cachePort->sendTiming(pkt);
-        cachePort->cache->sendResult(pkt, success);
+            cachePort->sendTiming(pkt);
+        }
         return;
     }
     //Know the packet to send, no need to mark in service (must succed)
-- 
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