From ddfa96cf455ba4a287930942514cdf0f7f2afa77 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Fri, 21 Aug 2015 07:03:23 -0400
Subject: mem: Add explicit Cache subclass and make BaseCache abstract

Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.

--HG--
rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
---
 src/mem/cache/cache.cc | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

(limited to 'src/mem/cache/cache.cc')

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 2426a0636..911785479 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -63,8 +63,8 @@
 #include "mem/cache/prefetch/base.hh"
 #include "sim/sim_exit.hh"
 
-Cache::Cache(const Params *p)
-    : BaseCache(p),
+Cache::Cache(const CacheParams *p)
+    : BaseCache(p, p->system->cacheLineSize()),
       tags(p->tags),
       prefetcher(p->prefetcher),
       doFastWrites(true),
@@ -2382,6 +2382,13 @@ CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
 {
 }
 
+Cache*
+CacheParams::create()
+{
+    assert(tags);
+
+    return new Cache(this);
+}
 ///////////////
 //
 // MemSidePort
-- 
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