From 3952e41ab1f1dfaa2f97a6a486528e4ea0bfc5a1 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@gmail.com>
Date: Wed, 2 Jan 2008 12:20:15 -0800
Subject: Add functional PrintReq command for memory-system debugging.

--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
---
 src/mem/cache/cache.hh | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/mem/cache/cache.hh')

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 037afd6ac..4602fd835 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -73,6 +73,7 @@ class Cache : public BaseCache
       public:
         CpuSidePort(const std::string &_name,
                     Cache<TagStore> *_cache,
+                    const std::string &_label,
                     std::vector<Range<Addr> > filterRanges);
 
         // BaseCache::CachePort just has a BaseCache *; this function
@@ -97,6 +98,7 @@ class Cache : public BaseCache
       public:
         MemSidePort(const std::string &_name,
                     Cache<TagStore> *_cache,
+                    const std::string &_label,
                     std::vector<Range<Addr> > filterRanges);
 
         // BaseCache::CachePort just has a BaseCache *; this function
@@ -229,7 +231,8 @@ class Cache : public BaseCache
      * @param pkt The request to perform.
      * @return The result of the access.
      */
-    void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
+    void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
+                          CachePort *otherSidePort);
 
     /**
      * Handles a response (cache line fill/write ack) from the bus.
-- 
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