From dea1a19b2de2fe031f714904c5247cf27b363237 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 30 Jun 2006 11:34:27 -0400 Subject: Fix the packet data allocation methods. Small fixes from changesets after my initial work. This now compiles. src/mem/cache/base_cache.cc: Fix getPort function that changed src/mem/cache/base_cache.hh: Fix get port function, provide default implementations of virtual functions in the base class src/mem/cache/cache.hh: Fix virtual function declerations src/mem/cache/cache_builder.cc: Fix params src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: Properly allocate data in packet --HG-- extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48 --- src/mem/cache/cache_builder.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mem/cache/cache_builder.cc') diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index 8758dc57a..05a149a1c 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -230,7 +230,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) Cache, b, c>::Params params(tagStore, mq, coh, \ do_copy, base_params, \ /*in_bus, out_bus,*/ pf, \ - prefetch_access); \ + prefetch_access, hit_latency); \ Cache, b, c> *retval = \ new Cache, b, c>(getInstanceName(), /*hier,*/ \ params); \ @@ -242,7 +242,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) retval->setMasterInterface(new MasterInterface, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \ out_bus->rangeChange(); \ return retval; \ -*/return true; \ +*/return retval; \ } while (0) #define BUILD_CACHE_PANIC(x) do { \ -- cgit v1.2.3