From 9117c94f9c74f0674d75731385a106d17a1dee09 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 27 Jun 2007 20:54:13 -0700 Subject: Get rid of coherence protocol object. --HG-- extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42 --- src/mem/cache/cache_impl.hh | 191 ++++++++++++++++++++++---------------------- 1 file changed, 96 insertions(+), 95 deletions(-) (limited to 'src/mem/cache/cache_impl.hh') diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 3685bc8cb..b76d7e392 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -48,13 +48,13 @@ #include "sim/sim_exit.hh" // for SimExitEvent -template -Cache::Cache(const std::string &_name, - Cache::Params ¶ms) +template +Cache::Cache(const std::string &_name, + Cache::Params ¶ms) : BaseCache(_name, params.baseParams), prefetchAccess(params.prefetchAccess), tags(params.tags), - coherence(params.coherence), prefetcher(params.prefetcher), + prefetcher(params.prefetcher), doFastWrites(params.doFastWrites), prefetchMiss(params.prefetchMiss) { @@ -67,23 +67,21 @@ Cache::Cache(const std::string &_name, memSidePort->setOtherPort(cpuSidePort); tags->setCache(this); - coherence->setCache(this); prefetcher->setCache(this); } -template +template void -Cache::regStats() +Cache::regStats() { BaseCache::regStats(); tags->regStats(name()); - coherence->regStats(name()); prefetcher->regStats(name()); } -template +template Port * -Cache::getPort(const std::string &if_name, int idx) +Cache::getPort(const std::string &if_name, int idx) { if (if_name == "" || if_name == "cpu_side") { return cpuSidePort; @@ -96,9 +94,9 @@ Cache::getPort(const std::string &if_name, int idx) } } -template +template void -Cache::deletePortRefs(Port *p) +Cache::deletePortRefs(Port *p) { if (cpuSidePort == p || memSidePort == p) panic("Can only delete functional ports\n"); @@ -107,9 +105,9 @@ Cache::deletePortRefs(Port *p) } -template +template void -Cache::cmpAndSwap(BlkType *blk, PacketPtr pkt) +Cache::cmpAndSwap(BlkType *blk, PacketPtr pkt) { uint64_t overwrite_val; bool overwrite_mem; @@ -152,9 +150,9 @@ Cache::cmpAndSwap(BlkType *blk, PacketPtr pkt) ///////////////////////////////////////////////////// -template +template void -Cache::markInService(MSHR *mshr) +Cache::markInService(MSHR *mshr) { markInServiceInternal(mshr); #if 0 @@ -171,9 +169,9 @@ Cache::markInService(MSHR *mshr) } -template +template void -Cache::squash(int threadNum) +Cache::squash(int threadNum) { bool unblock = false; BlockedCause cause = NUM_BLOCKED_CAUSES; @@ -199,9 +197,9 @@ Cache::squash(int threadNum) // ///////////////////////////////////////////////////// -template +template bool -Cache::access(PacketPtr pkt, BlkType *&blk, int &lat) +Cache::access(PacketPtr pkt, BlkType *&blk, int &lat) { if (pkt->req->isUncacheable()) { blk = NULL; @@ -280,9 +278,9 @@ Cache::access(PacketPtr pkt, BlkType *&blk, int &lat) } -template +template bool -Cache::timingAccess(PacketPtr pkt) +Cache::timingAccess(PacketPtr pkt) { //@todo Add back in MemDebug Calls // MemDebug::cacheAccess(pkt); @@ -398,10 +396,10 @@ Cache::timingAccess(PacketPtr pkt) } -template +template PacketPtr -Cache::getBusPacket(PacketPtr cpu_pkt, BlkType *blk, - bool needsExclusive) +Cache::getBusPacket(PacketPtr cpu_pkt, BlkType *blk, + bool needsExclusive) { bool blkValid = blk && blk->isValid(); @@ -441,9 +439,9 @@ Cache::getBusPacket(PacketPtr cpu_pkt, BlkType *blk, } -template +template Tick -Cache::atomicAccess(PacketPtr pkt) +Cache::atomicAccess(PacketPtr pkt) { int lat = hitLatency; @@ -511,10 +509,10 @@ Cache::atomicAccess(PacketPtr pkt) } -template +template void -Cache::functionalAccess(PacketPtr pkt, - CachePort *otherSidePort) +Cache::functionalAccess(PacketPtr pkt, + CachePort *otherSidePort) { Addr blk_addr = pkt->getAddr() & ~(blkSize - 1); BlkType *blk = tags->findBlock(pkt->getAddr()); @@ -561,9 +559,9 @@ Cache::functionalAccess(PacketPtr pkt, ///////////////////////////////////////////////////// -template +template void -Cache::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk) +Cache::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk) { assert(blk); assert(pkt->needsExclusive() ? blk->isWritable() : blk->isValid()); @@ -586,10 +584,10 @@ Cache::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk) } -template +template bool -Cache::satisfyMSHR(MSHR *mshr, PacketPtr pkt, - BlkType *blk) +Cache::satisfyMSHR(MSHR *mshr, PacketPtr pkt, + BlkType *blk) { // respond to MSHR targets, if any @@ -642,9 +640,9 @@ Cache::satisfyMSHR(MSHR *mshr, PacketPtr pkt, } -template +template void -Cache::handleResponse(PacketPtr pkt) +Cache::handleResponse(PacketPtr pkt) { Tick time = curTick + hitLatency; MSHR *mshr = dynamic_cast(pkt->senderState); @@ -730,9 +728,9 @@ Cache::handleResponse(PacketPtr pkt) -template +template PacketPtr -Cache::writebackBlk(BlkType *blk) +Cache::writebackBlk(BlkType *blk) { assert(blk && blk->isValid() && blk->isDirty()); @@ -754,12 +752,13 @@ Cache::writebackBlk(BlkType *blk) // is called by both atomic and timing-mode accesses, and in atomic // mode we don't mess with the write buffer (we just perform the // writebacks atomically once the original request is complete). -template -typename Cache::BlkType* -Cache::handleFill(PacketPtr pkt, BlkType *blk, - PacketList &writebacks) +template +typename Cache::BlkType* +Cache::handleFill(PacketPtr pkt, BlkType *blk, + PacketList &writebacks) { Addr addr = pkt->getAddr(); + CacheBlk::State old_state = blk ? blk->status : 0; if (blk == NULL) { // better have read new data... @@ -795,21 +794,24 @@ Cache::handleFill(PacketPtr pkt, BlkType *blk, } blk->tag = tags->extractTag(addr); - blk->status = coherence->getNewState(pkt); } else { // existing block... probably an upgrade assert(blk->tag == tags->extractTag(addr)); // either we're getting new data or the block should already be valid assert(pkt->isRead() || blk->isValid()); - CacheBlk::State old_state = blk->status; - blk->status = coherence->getNewState(pkt, old_state); - if (blk->status != old_state) - DPRINTF(Cache, "Block addr %x moving from state %i to %i\n", - addr, old_state, blk->status); - else - warn("Changing state to same value\n"); } + if (pkt->needsExclusive()) { + blk->status = BlkValid | BlkWritable | BlkDirty; + } else if (!pkt->sharedAsserted()) { + blk->status = BlkValid | BlkWritable; + } else { + blk->status = BlkValid; + } + + DPRINTF(Cache, "Block addr %x moving from state %i to %i\n", + addr, old_state, blk->status); + // if we got new data, copy it in if (pkt->isRead()) { std::memcpy(blk->data, pkt->getPtr(), blkSize); @@ -827,11 +829,11 @@ Cache::handleFill(PacketPtr pkt, BlkType *blk, // ///////////////////////////////////////////////////// -template +template void -Cache::doTimingSupplyResponse(PacketPtr req_pkt, - uint8_t *blk_data, - bool already_copied) +Cache::doTimingSupplyResponse(PacketPtr req_pkt, + uint8_t *blk_data, + bool already_copied) { // timing-mode snoop responses require a new packet, unless we // already made a copy... @@ -842,10 +844,10 @@ Cache::doTimingSupplyResponse(PacketPtr req_pkt, memSidePort->respond(pkt, curTick + hitLatency); } -template +template void -Cache::handleSnoop(PacketPtr pkt, BlkType *blk, - bool is_timing, bool is_deferred) +Cache::handleSnoop(PacketPtr pkt, BlkType *blk, + bool is_timing, bool is_deferred) { if (!blk || !blk->isValid()) { return; @@ -894,9 +896,9 @@ Cache::handleSnoop(PacketPtr pkt, BlkType *blk, } -template +template void -Cache::snoopTiming(PacketPtr pkt) +Cache::snoopTiming(PacketPtr pkt) { if (pkt->req->isUncacheable()) { //Can't get a hit on an uncacheable address @@ -959,9 +961,9 @@ Cache::snoopTiming(PacketPtr pkt) } -template +template Tick -Cache::snoopAtomic(PacketPtr pkt) +Cache::snoopAtomic(PacketPtr pkt) { if (pkt->req->isUncacheable()) { // Can't get a hit on an uncacheable address @@ -975,9 +977,9 @@ Cache::snoopAtomic(PacketPtr pkt) } -template +template MSHR * -Cache::getNextMSHR() +Cache::getNextMSHR() { // Check both MSHR queue and write buffer for potential requests MSHR *miss_mshr = mshrQueue.getNextMSHR(); @@ -1051,9 +1053,9 @@ Cache::getNextMSHR() } -template +template PacketPtr -Cache::getTimingPacket() +Cache::getTimingPacket() { MSHR *mshr = getNextMSHR(); @@ -1100,9 +1102,9 @@ Cache::getTimingPacket() // /////////////// -template +template void -Cache::CpuSidePort:: +Cache::CpuSidePort:: getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) { // CPU side port doesn't snoop; it's a target only. @@ -1112,9 +1114,9 @@ getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) } -template +template bool -Cache::CpuSidePort::recvTiming(PacketPtr pkt) +Cache::CpuSidePort::recvTiming(PacketPtr pkt) { if (pkt->isRequest() && blocked) { DPRINTF(Cache,"Scheduling a retry while blocked\n"); @@ -1127,17 +1129,17 @@ Cache::CpuSidePort::recvTiming(PacketPtr pkt) } -template +template Tick -Cache::CpuSidePort::recvAtomic(PacketPtr pkt) +Cache::CpuSidePort::recvAtomic(PacketPtr pkt) { return myCache()->atomicAccess(pkt); } -template +template void -Cache::CpuSidePort::recvFunctional(PacketPtr pkt) +Cache::CpuSidePort::recvFunctional(PacketPtr pkt) { checkFunctional(pkt); if (pkt->result != Packet::Success) @@ -1145,10 +1147,10 @@ Cache::CpuSidePort::recvFunctional(PacketPtr pkt) } -template -Cache:: +template +Cache:: CpuSidePort::CpuSidePort(const std::string &_name, - Cache *_cache) + Cache *_cache) : BaseCache::CachePort(_name, _cache) { } @@ -1159,9 +1161,9 @@ CpuSidePort::CpuSidePort(const std::string &_name, // /////////////// -template +template void -Cache::MemSidePort:: +Cache::MemSidePort:: getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) { otherPort->getPeerAddressRanges(resp, snoop); @@ -1171,9 +1173,9 @@ getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) } -template +template bool -Cache::MemSidePort::recvTiming(PacketPtr pkt) +Cache::MemSidePort::recvTiming(PacketPtr pkt) { // this needs to be fixed so that the cache updates the mshr and sends the // packet back out on the link, but it probably won't happen so until this @@ -1196,9 +1198,9 @@ Cache::MemSidePort::recvTiming(PacketPtr pkt) } -template +template Tick -Cache::MemSidePort::recvAtomic(PacketPtr pkt) +Cache::MemSidePort::recvAtomic(PacketPtr pkt) { // in atomic mode, responses go back to the sender via the // function return from sendAtomic(), not via a separate @@ -1209,9 +1211,9 @@ Cache::MemSidePort::recvAtomic(PacketPtr pkt) } -template +template void -Cache::MemSidePort::recvFunctional(PacketPtr pkt) +Cache::MemSidePort::recvFunctional(PacketPtr pkt) { checkFunctional(pkt); if (pkt->result != Packet::Success) @@ -1220,9 +1222,9 @@ Cache::MemSidePort::recvFunctional(PacketPtr pkt) -template +template void -Cache::MemSidePort::sendPacket() +Cache::MemSidePort::sendPacket() { // if we have responses that are ready, they take precedence if (deferredPacketReady()) { @@ -1278,28 +1280,27 @@ Cache::MemSidePort::sendPacket() } } -template +template void -Cache::MemSidePort::recvRetry() +Cache::MemSidePort::recvRetry() { assert(waitingOnRetry); sendPacket(); } -template +template void -Cache::MemSidePort::processSendEvent() +Cache::MemSidePort::processSendEvent() { assert(!waitingOnRetry); sendPacket(); } -template -Cache:: -MemSidePort::MemSidePort(const std::string &_name, - Cache *_cache) +template +Cache:: +MemSidePort::MemSidePort(const std::string &_name, Cache *_cache) : BaseCache::CachePort(_name, _cache) { // override default send event from SimpleTimingPort -- cgit v1.2.3