From de62aedabc96e7492c40bbc4468ba42b3274bfd6 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Sat, 27 Sep 2014 09:08:29 -0400
Subject: misc: Fix a bunch of minor issues identified by static analysis

Add some missing initialisation, and fix a handful benign resource
leaks (including some false positives).
---
 src/mem/cache/cache_impl.hh | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mem/cache/cache_impl.hh')

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index e4a6f3c24..5cfe7c0cf 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -917,6 +917,9 @@ Cache<TagStore>::recvAtomic(PacketPtr pkt)
     if (pkt->cmd == MemCmd::WriteInvalidateReq) {
         memSidePort->sendAtomic(pkt); // complete writeback
         if (isTopLevel) {
+            // @todo Static analysis suggests this can actually happen
+            assert(blk);
+
             // top level caches allocate and write the data
             assert(blk->isDirty());
             assert(!blk->isWritable());
-- 
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