From a17afb1649e26c248dc4a61e4a0ef6671785e992 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 13 Oct 2006 15:47:05 -0400 Subject: Fix for DMA's in FS caches. Fix CSHR's for flow control. Fix for Bus Bridges reusing packets (clean flags up) Now both timing/atomic caches with MOESI in UP fail at same point. src/dev/io_device.hh: DMA's should send WriteInvalidates src/mem/bridge.cc: Reusing packet, clean flags in the packet set by bus. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Fix CSHR's for flow control. src/mem/packet.hh: Make a writeInvalidateResp, since the DMA expects responses to it's writes --HG-- extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd --- src/mem/cache/coherence/simple_coherence.hh | 12 ++++++++++++ src/mem/cache/coherence/uni_coherence.cc | 30 +++++++++++++++++++---------- src/mem/cache/coherence/uni_coherence.hh | 8 ++++++++ 3 files changed, 40 insertions(+), 10 deletions(-) (limited to 'src/mem/cache/coherence') diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh index 71d8f36f4..a356b3ecc 100644 --- a/src/mem/cache/coherence/simple_coherence.hh +++ b/src/mem/cache/coherence/simple_coherence.hh @@ -94,6 +94,18 @@ class SimpleCoherence return NULL; } + /** + * Was the CSHR request was sent successfully? + * @param pkt The request. + * @param success True if the request was sent successfully. + */ + void sendResult(Packet * &pkt, MSHR* cshr, bool success) + { + //Don't do coherence + return; + } + + /** * Return the proper state given the current state and the bus response. * @param pkt The bus response. diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc index 0efe393f9..751de4801 100644 --- a/src/mem/cache/coherence/uni_coherence.cc +++ b/src/mem/cache/coherence/uni_coherence.cc @@ -43,20 +43,30 @@ UniCoherence::UniCoherence() Packet * UniCoherence::getPacket() { - bool unblock = cshrs.isFull(); Packet* pkt = cshrs.getReq(); - cshrs.markInService((MSHR*)pkt->senderState); - if (!cshrs.havePending()) { - cache->clearSlaveRequest(Request_Coherence); - } - if (unblock) { - //since CSHRs are always used as buffers, should always get rid of one - assert(!cshrs.isFull()); - cache->clearBlocked(Blocked_Coherence); - } return pkt; } +void +UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success) +{ + if (success) + { + bool unblock = cshrs.isFull(); + cshrs.markInService(cshr); + if (!cshrs.havePending()) { + cache->clearSlaveRequest(Request_Coherence); + } + cshrs.deallocate(cshr); + if (unblock) { + //since CSHRs are always used as buffers, should always get rid of one + assert(!cshrs.isFull()); + cache->clearBlocked(Blocked_Coherence); + } + } +} + + /** * @todo add support for returning slave requests, not doing them here. */ diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh index 27b6c7fb5..60da7a36e 100644 --- a/src/mem/cache/coherence/uni_coherence.hh +++ b/src/mem/cache/coherence/uni_coherence.hh @@ -108,12 +108,20 @@ class UniCoherence else return BlkValid | BlkWritable; } + /** * Return outstanding invalidate to forward. * @return The next invalidate to forward to lower levels of cache. */ Packet * getPacket(); + /** + * Was the CSHR request was sent successfully? + * @param pkt The request. + * @param success True if the request was sent successfully. + */ + void sendResult(Packet * &pkt, MSHR* cshr, bool success); + /** * Handle snooped bus requests. * @param pkt The snooped bus request. -- cgit v1.2.3