From d5ac1cb51f2e08531794e1dcbb17e47f51041c4f Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Tue, 15 Aug 2006 16:21:46 -0400 Subject: Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches. -Basically removed the ASID from places it is no longer needed due to PageTable src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/prefetch/base_prefetcher.hh: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: Remove asid where it wasn't neccesary anymore due to Page Table --HG-- extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28 --- src/mem/cache/miss/blocking_buffer.cc | 6 +++--- src/mem/cache/miss/blocking_buffer.hh | 10 +++++----- src/mem/cache/miss/miss_queue.cc | 22 +++++++++++----------- src/mem/cache/miss/miss_queue.hh | 10 +++++----- src/mem/cache/miss/mshr.cc | 7 +++---- src/mem/cache/miss/mshr.hh | 2 +- src/mem/cache/miss/mshr_queue.cc | 14 +++++++------- src/mem/cache/miss/mshr_queue.hh | 8 ++++---- 8 files changed, 39 insertions(+), 40 deletions(-) (limited to 'src/mem/cache/miss') diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index 2f61e8a54..67fc7ae56 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -76,7 +76,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) if (!pkt->needsResponse()) { wb.allocateAsBuffer(pkt); } else { - wb.allocate(pkt->cmd, blk_addr, pkt->req->getAsid(), blk_size, pkt); + wb.allocate(pkt->cmd, blk_addr, blk_size, pkt); } memcpy(wb.pkt->getPtr(), pkt->getPtr(), blk_size); @@ -89,7 +89,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) if (!pkt->needsResponse()) { miss.allocateAsBuffer(pkt); } else { - miss.allocate(pkt->cmd, blk_addr, pkt->req->getAsid(), blk_size, pkt); + miss.allocate(pkt->cmd, blk_addr, blk_size, pkt); } if (!pkt->req->isUncacheable()) { miss.pkt->flags |= CACHE_LINE_FILL; @@ -202,7 +202,7 @@ BlockingBuffer::squash(int threadNum) } void -BlockingBuffer::doWriteback(Addr addr, int asid, +BlockingBuffer::doWriteback(Addr addr, int size, uint8_t *data, bool compressed) { // Generate request diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh index a6261f62c..641d5a798 100644 --- a/src/mem/cache/miss/blocking_buffer.hh +++ b/src/mem/cache/miss/blocking_buffer.hh @@ -121,7 +121,7 @@ public: * @param time The time the miss is detected. * @param target The target for the fetch. */ - MSHR* fetchBlock(Addr addr, int asid, int blk_size, Tick time, + MSHR* fetchBlock(Addr addr, int blk_size, Tick time, Packet * &target) { fatal("Unimplemented"); @@ -183,7 +183,7 @@ public: * @param asid The address space id. * @return A pointer to miss if it matches. */ - MSHR* findMSHR(Addr addr, int asid) + MSHR* findMSHR(Addr addr) { if (miss.addr == addr && miss.pkt) return &miss; @@ -197,7 +197,7 @@ public: * @param writes List of pointers to the matching writes. * @return True if there is a matching write. */ - bool findWrites(Addr addr, int asid, std::vector& writes) + bool findWrites(Addr addr, std::vector& writes) { if (wb.addr == addr && wb.pkt) { writes.push_back(&wb); @@ -216,7 +216,7 @@ public: * @param data The data to write, can be NULL. * @param compressed True if the data is compressed. */ - void doWriteback(Addr addr, int asid, + void doWriteback(Addr addr, int size, uint8_t *data, bool compressed); /** @@ -247,7 +247,7 @@ public: /** * Dummy implmentation. */ - MSHR* allocateTargetList(Addr addr, int asid) + MSHR* allocateTargetList(Addr addr) { fatal("Unimplemented"); } diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index 4a3dc1062..76fb25716 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -410,7 +410,7 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1); MSHR* mshr = NULL; if (!pkt->req->isUncacheable()) { - mshr = mq.findMatch(blkAddr, pkt->req->getAsid()); + mshr = mq.findMatch(blkAddr); if (mshr) { //@todo remove hw_pf here mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; @@ -454,12 +454,12 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) } MSHR* -MissQueue::fetchBlock(Addr addr, int asid, int blk_size, Tick time, +MissQueue::fetchBlock(Addr addr, int blk_size, Tick time, Packet * &target) { Addr blkAddr = addr & ~(Addr)(blk_size - 1); - assert(mq.findMatch(addr, asid) == NULL); - MSHR *mshr = mq.allocateFetch(blkAddr, asid, blk_size, target); + assert(mq.findMatch(addr) == NULL); + MSHR *mshr = mq.allocateFetch(blkAddr, blk_size, target); mshr->order = order++; mshr->pkt->flags |= CACHE_LINE_FILL; if (mq.isFull()) { @@ -697,19 +697,19 @@ MissQueue::squash(int threadNum) } MSHR* -MissQueue::findMSHR(Addr addr, int asid) const +MissQueue::findMSHR(Addr addr) const { - return mq.findMatch(addr,asid); + return mq.findMatch(addr); } bool -MissQueue::findWrites(Addr addr, int asid, vector &writes) const +MissQueue::findWrites(Addr addr, vector &writes) const { - return wb.findMatches(addr,asid,writes); + return wb.findMatches(addr,writes); } void -MissQueue::doWriteback(Addr addr, int asid, +MissQueue::doWriteback(Addr addr, int size, uint8_t *data, bool compressed) { // Generate request @@ -740,9 +740,9 @@ MissQueue::doWriteback(Packet * &pkt) MSHR* -MissQueue::allocateTargetList(Addr addr, int asid) +MissQueue::allocateTargetList(Addr addr) { - MSHR* mshr = mq.allocateTargetList(addr, asid, blkSize); + MSHR* mshr = mq.allocateTargetList(addr, blkSize); mshr->pkt->flags |= CACHE_LINE_FILL; if (mq.isFull()) { cache->setBlocked(Blocked_NoMSHRs); diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh index c558df956..505d1f90c 100644 --- a/src/mem/cache/miss/miss_queue.hh +++ b/src/mem/cache/miss/miss_queue.hh @@ -228,7 +228,7 @@ class MissQueue * @param time The time the miss is detected. * @param target The target for the fetch. */ - MSHR* fetchBlock(Addr addr, int asid, int blk_size, Tick time, + MSHR* fetchBlock(Addr addr, int blk_size, Tick time, Packet * &target); /** @@ -289,7 +289,7 @@ class MissQueue * @warning Currently only searches the miss queue. If non write allocate * might need to search the write buffer for coherence. */ - MSHR* findMSHR(Addr addr, int asid) const; + MSHR* findMSHR(Addr addr) const; /** * Searches for the supplied address in the write buffer. @@ -298,7 +298,7 @@ class MissQueue * @param writes The list of writes that match the address. * @return True if any writes are found */ - bool findWrites(Addr addr, int asid, std::vector& writes) const; + bool findWrites(Addr addr, std::vector& writes) const; /** * Perform a writeback of dirty data to the given address. @@ -309,7 +309,7 @@ class MissQueue * @param data The data to write, can be NULL. * @param compressed True if the data is compressed. */ - void doWriteback(Addr addr, int asid, + void doWriteback(Addr addr, int size, uint8_t *data, bool compressed); /** @@ -342,7 +342,7 @@ class MissQueue * @param asid The address space ID. * @return A pointer to the allocated MSHR. */ - MSHR* allocateTargetList(Addr addr, int asid); + MSHR* allocateTargetList(Addr addr); }; diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index db2f40c56..64bcbb833 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -54,7 +54,7 @@ MSHR::MSHR() } void -MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size, +MSHR::allocate(Packet::Command cmd, Addr _addr, int size, Packet * &target) { addr = _addr; @@ -88,7 +88,6 @@ void MSHR::allocateAsBuffer(Packet * &target) { addr = target->getAddr(); - asid = target->req->getAsid(); threadNum = target->req->getThreadNum(); pkt = new Packet(target->req, target->cmd, -1); pkt->allocate(); @@ -159,9 +158,9 @@ MSHR::dump() { ccprintf(cerr, "inService: %d thread: %d\n" - "Addr: %x asid: %d ntargets %d\n" + "Addr: %x ntargets %d\n" "Targets:\n", - inService, threadNum, addr, asid, ntargets); + inService, threadNum, addr, ntargets); TargetListIterator tar_it = targets.begin(); for (int i = 0; i < ntargets; i++) { diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh index ad2865973..028259b35 100644 --- a/src/mem/cache/miss/mshr.hh +++ b/src/mem/cache/miss/mshr.hh @@ -100,7 +100,7 @@ public: * @param size The number of bytes to pktuest. * @param pkt The original miss. */ - void allocate(Packet::Command cmd, Addr addr, int asid, int size, + void allocate(Packet::Command cmd, Addr addr, int size, Packet * &pkt); /** diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index 6516a99f8..f13f48dec 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -55,7 +55,7 @@ MSHRQueue::~MSHRQueue() } MSHR* -MSHRQueue::findMatch(Addr addr, int asid) const +MSHRQueue::findMatch(Addr addr) const { MSHR::ConstIterator i = allocatedList.begin(); MSHR::ConstIterator end = allocatedList.end(); @@ -69,7 +69,7 @@ MSHRQueue::findMatch(Addr addr, int asid) const } bool -MSHRQueue::findMatches(Addr addr, int asid, vector& matches) const +MSHRQueue::findMatches(Addr addr, vector& matches) const { // Need an empty vector assert(matches.empty()); @@ -136,7 +136,7 @@ MSHRQueue::allocate(Packet * &pkt, int size) mshr->allocateAsBuffer(pkt); } else { assert(size !=0); - mshr->allocate(pkt->cmd, aligned_addr, pkt->req->getAsid(), size, pkt); + mshr->allocate(pkt->cmd, aligned_addr, size, pkt); allocatedTargets += 1; } mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); @@ -147,12 +147,12 @@ MSHRQueue::allocate(Packet * &pkt, int size) } MSHR* -MSHRQueue::allocateFetch(Addr addr, int asid, int size, Packet * &target) +MSHRQueue::allocateFetch(Addr addr, int size, Packet * &target) { MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); - mshr->allocate(Packet::ReadReq, addr, asid, size, target); + mshr->allocate(Packet::ReadReq, addr, size, target); mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); mshr->readyIter = pendingList.insert(pendingList.end(), mshr); @@ -161,13 +161,13 @@ MSHRQueue::allocateFetch(Addr addr, int asid, int size, Packet * &target) } MSHR* -MSHRQueue::allocateTargetList(Addr addr, int asid, int size) +MSHRQueue::allocateTargetList(Addr addr, int size) { MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); Packet * dummy; - mshr->allocate(Packet::ReadReq, addr, asid, size, dummy); + mshr->allocate(Packet::ReadReq, addr, size, dummy); mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); mshr->inService = true; ++inServiceMSHRs; diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh index 02b6a026d..ea5f101b7 100644 --- a/src/mem/cache/miss/mshr_queue.hh +++ b/src/mem/cache/miss/mshr_queue.hh @@ -90,7 +90,7 @@ class MSHRQueue { * @param asid The address space id. * @return Pointer to the matching MSHR, null if not found. */ - MSHR* findMatch(Addr addr, int asid) const; + MSHR* findMatch(Addr addr) const; /** * Find and return all the matching MSHRs in the provided vector. @@ -100,7 +100,7 @@ class MSHRQueue { * @return True if any matches are found, false otherwise. * @todo Typedef the vector?? */ - bool findMatches(Addr addr, int asid, std::vector& matches) const; + bool findMatches(Addr addr, std::vector& matches) const; /** * Find any pending pktuests that overlap the given request. @@ -129,7 +129,7 @@ class MSHRQueue { * @param target The first target for the pktuest. * @return Pointer to the new MSHR. */ - MSHR* allocateFetch(Addr addr, int asid, int size, Packet * &target); + MSHR* allocateFetch(Addr addr, int size, Packet * &target); /** * Allocate a target list for the given address. @@ -138,7 +138,7 @@ class MSHRQueue { * @param size The number of bytes to pktuest. * @return Pointer to the new MSHR. */ - MSHR* allocateTargetList(Addr addr, int asid, int size); + MSHR* allocateTargetList(Addr addr, int size); /** * Removes the given MSHR from the queue. This places the MSHR on the -- cgit v1.2.3