From 71aca6d29e686ecdec2828c8be1989f74d9b28d3 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Thu, 9 Sep 2010 14:40:18 -0400
Subject: cache: coherence protocol enhancements & bug fixes Allow lower-level
 caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1).
  This eliminates a lot of unnecessary upgrade transactions on read-write
 sequences to non-shared data.

Also some cleanup of MSHR coherence handling and multiple
bug fixes.
---
 src/mem/cache/mshr_queue.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mem/cache/mshr_queue.hh')

diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index f481ca471..d8c495679 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -160,7 +160,7 @@ class MSHRQueue
      * readyList. Deallocates the MSHR if it does not expect a response.
      * @param mshr The MSHR to mark in service.
      */
-    void markInService(MSHR *mshr);
+    void markInService(MSHR *mshr, PacketPtr pkt);
 
     /**
      * Mark an in service entry as pending, used to resend a request.
-- 
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