From 8590243fef2e4ccaefde3af767496dec44c6eb33 Mon Sep 17 00:00:00 2001
From: Javier Bueno <javier.bueno@metempsy.com>
Date: Fri, 9 Nov 2018 16:02:04 +0100
Subject: mem-cache: implement a probe-based interface

The HW Prefetcher of a cache can now listen events
from their associated CPUs and from its own cache.

Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3
Reviewed-on: https://gem5-review.googlesource.com/c/14155
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
 src/mem/cache/prefetch/queued.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'src/mem/cache/prefetch/queued.cc')

diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index 3c5647ae3..f9a036d45 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -63,7 +63,7 @@ QueuedPrefetcher::~QueuedPrefetcher()
     }
 }
 
-Tick
+void
 QueuedPrefetcher::notify(const PacketPtr &pkt)
 {
     // Verify this access type is observed by prefetcher
@@ -110,8 +110,6 @@ QueuedPrefetcher::notify(const PacketPtr &pkt)
             }
         }
     }
-
-    return pfq.empty() ? MaxTick : pfq.front().tick;
 }
 
 PacketPtr
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