From d5ac1cb51f2e08531794e1dcbb17e47f51041c4f Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 15 Aug 2006 16:21:46 -0400
Subject: Pulled out changes to fix EIO programs with caches.  Also fixes any
 translatingPort read/write Blob function problems with caches.

-Basically removed the ASID from places it is no longer needed due to PageTable

src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
    Remove asid where it wasn't neccesary anymore due to Page Table

--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
---
 src/mem/cache/prefetch/base_prefetcher.cc | 2 +-
 src/mem/cache/prefetch/base_prefetcher.hh | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mem/cache/prefetch')

diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc
index 897551989..5e50c48bd 100644
--- a/src/mem/cache/prefetch/base_prefetcher.cc
+++ b/src/mem/cache/prefetch/base_prefetcher.cc
@@ -198,7 +198,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
             }
 
             //Check if it is already in the miss_queue
-            if (inMissQueue(prefetch->getAddr(), prefetch->req->getAsid())) {
+            if (inMissQueue(prefetch->getAddr())) {
                 addr++;
                 delay++;
                 continue;
diff --git a/src/mem/cache/prefetch/base_prefetcher.hh b/src/mem/cache/prefetch/base_prefetcher.hh
index 3e4fc89d1..d7ea41961 100644
--- a/src/mem/cache/prefetch/base_prefetcher.hh
+++ b/src/mem/cache/prefetch/base_prefetcher.hh
@@ -108,7 +108,7 @@ class BasePrefetcher
 
     virtual bool inCache(Packet * &pkt) = 0;
 
-    virtual bool inMissQueue(Addr address, int asid) = 0;
+    virtual bool inMissQueue(Addr address) = 0;
 
     std::list<Packet *>::iterator inPrefetch(Addr address);
 };
-- 
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