From 56865ad1154c7c3fde2ae6b7329d0c888390f781 Mon Sep 17 00:00:00 2001
From: Nikos Nikoleris <nikos.nikoleris@arm.com>
Date: Thu, 3 May 2018 12:14:41 +0100
Subject: mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
 src/mem/cache/write_queue_entry.cc | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'src/mem/cache/write_queue_entry.cc')

diff --git a/src/mem/cache/write_queue_entry.cc b/src/mem/cache/write_queue_entry.cc
index 4aa174b5a..e393731b7 100644
--- a/src/mem/cache/write_queue_entry.cc
+++ b/src/mem/cache/write_queue_entry.cc
@@ -50,16 +50,13 @@
 
 #include "mem/cache/write_queue_entry.hh"
 
-#include <algorithm>
 #include <cassert>
 #include <string>
-#include <vector>
 
 #include "base/logging.hh"
 #include "base/types.hh"
-#include "debug/Cache.hh"
-#include "mem/cache/cache.hh"
-#include "sim/core.hh"
+#include "mem/cache/base.hh"
+#include "mem/request.hh"
 
 inline void
 WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
-- 
cgit v1.2.3