From 0b3897fc90901953e9d016466c37ab507f85023c Mon Sep 17 00:00:00 2001 From: Anthony Gutierrez Date: Wed, 15 Aug 2012 10:38:08 -0400 Subject: O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation. --- src/mem/cache/base.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mem/cache') diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 4ae6376db..c175d5958 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -48,6 +48,7 @@ #include "cpu/base.hh" #include "cpu/smt.hh" #include "debug/Cache.hh" +#include "debug/Drain.hh" #include "mem/cache/base.hh" #include "mem/cache/mshr.hh" #include "sim/full_system.hh" @@ -752,6 +753,7 @@ BaseCache::drain(Event *de) drainEvent = de; changeState(SimObject::Draining); + DPRINTF(Drain, "Cache not drained\n"); return count; } -- cgit v1.2.3