From 1ccfdb442ff34f9f2b38ee7716b7baee99a397c2 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Thu, 6 Jul 2006 16:52:05 -0400
Subject: Timing cache works for hello world test. Still need 1) detailed CPU
 (blocking ability in cache) 1a) Multiple outstanding requests (need to keep
 track of times for events) 2)Multi-level support 3)MP coherece support
 4)LL/SC support 5)Functional path needs to be correctly implemented
 (temporarily works without multiple outstanding requests (simple cpu))

src/cpu/simple/timing.cc:
    Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
    Handle marking MSHR's in service
    Add support for getting CSHR's
src/mem/cache/base_cache.hh:
    Make these functions visible at the base cache level
src/mem/cache/cache.hh:
    make the functions virtual
src/mem/cache/cache_impl.hh:
    Rename the function to make sense
src/mem/packet.hh:
    Accidentally clearing the needsResponse field when sending a response back.

--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
---
 src/mem/cache/base_cache.cc | 10 ++++++++--
 src/mem/cache/base_cache.hh | 11 +++++++++++
 src/mem/cache/cache.hh      |  4 ++--
 src/mem/cache/cache_impl.hh |  2 +-
 4 files changed, 22 insertions(+), 5 deletions(-)

(limited to 'src/mem/cache')

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 15a21efa1..4fbda4074 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -118,9 +118,15 @@ BaseCache::CacheEvent::process()
     {
         if (!cachePort->isCpuSide)
             pkt = cachePort->cache->getPacket();
-        //Else get coherence req
+        else
+            pkt = cachePort->cache->getCoherencePacket();
+        bool success = cachePort->sendTiming(pkt);
+        cachePort->cache->sendResult(pkt, success);
+        return;
     }
-    cachePort->sendTiming(pkt);
+    //Know the packet to send, no need to mark in service (must succed)
+    bool success = cachePort->sendTiming(pkt);
+    assert(success);
 }
 
 const char *
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 5370a73c8..f832735db 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -153,6 +153,17 @@ class BaseCache : public MemObject
         fatal("No implementation");
     }
 
+    virtual Packet *getCoherencePacket()
+    {
+        fatal("No implementation");
+    }
+
+    virtual void sendResult(Packet* &pkt, bool success)
+    {
+
+        fatal("No implementation");
+    }
+
     /**
      * Bit vector of the blocking reasons for the access path.
      * @sa #BlockedCause
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 2e77444a0..ec5b800a8 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -175,7 +175,7 @@ class Cache : public BaseCache
      * @param req The request.
      * @param success True if the request was sent successfully.
      */
-    void sendResult(Packet * &pkt, bool success);
+    virtual void sendResult(Packet * &pkt, bool success);
 
     /**
      * Handles a response (cache line fill/write ack) from the bus.
@@ -202,7 +202,7 @@ class Cache : public BaseCache
      * Selects a coherence message to forward to lower levels of the hierarchy.
      * @return The coherence message to forward.
      */
-    Packet * getCoherenceReq();
+    virtual Packet * getCoherencePacket();
 
     /**
      * Snoops bus transactions to maintain coherence.
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index aae5cbf01..a447ae3d5 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -350,7 +350,7 @@ Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 
 template<class TagStore, class Buffering, class Coherence>
 Packet *
-Cache<TagStore,Buffering,Coherence>::getCoherenceReq()
+Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 {
     return coherence->getPacket();
 }
-- 
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