From 2a740aa09682c32eb8f1f8880f279c943d8c6ee1 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:12:35 -0400 Subject: Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default. --- src/mem/cache/base.cc | 8 ++++---- src/mem/cache/base.hh | 6 ++++-- 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'src/mem/cache') diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index c95999f3e..a88749627 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -118,8 +118,8 @@ BaseCache::init() cpuSidePort->sendRangeChange(); } -MasterPort & -BaseCache::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +BaseCache::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "mem_side") { return *memSidePort; @@ -128,8 +128,8 @@ BaseCache::getMasterPort(const std::string &if_name, int idx) } } -SlavePort & -BaseCache::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort & +BaseCache::getSlavePort(const std::string &if_name, PortID idx) { if (if_name == "cpu_side") { return *cpuSidePort; diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 2e31836c0..42ade9b0b 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -430,8 +430,10 @@ class BaseCache : public MemObject virtual void init(); - virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1); - virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); + virtual BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Query block size of a cache. -- cgit v1.2.3