From 407233f5d80d04e27234eb70750a7f6ee13acd4f Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Mon, 15 Feb 2016 03:40:04 -0500
Subject: mem: Avoid using invalid iterator in cache lock list traversal

Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
---
 src/mem/cache/blk.hh | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/mem/cache')

diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 6682dd4bb..39d45d6e1 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -347,15 +347,16 @@ class CacheBlk
             bool success = false;
 
             auto l = lockList.begin();
-            while (l != lockList.end() && !success) {
+            while (!success && l != lockList.end()) {
                 if (l->matches(pkt->req)) {
                     // it's a store conditional, and as far as the
                     // memory system can tell, the requesting
                     // context's lock is still valid.
                     success = true;
                     lockList.erase(l);
+                } else {
+                    ++l;
                 }
-                ++l;
             }
 
             req->setExtraData(success ? 1 : 0);
-- 
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