From c0ab52799ca4ebd0a51363cfedd0658e6d79b842 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Fri, 2 Nov 2012 11:32:01 -0500 Subject: sim: Include object header files in SWIG interfaces When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. --- src/mem/cache/BaseCache.py | 1 + src/mem/cache/prefetch/Prefetcher.py | 4 ++++ src/mem/cache/tags/iic_repl/Repl.py | 2 ++ 3 files changed, 7 insertions(+) (limited to 'src/mem/cache') diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 6fe73a9c2..fe0d9ceb0 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -46,6 +46,7 @@ from Prefetcher import BasePrefetcher class BaseCache(MemObject): type = 'BaseCache' + cxx_header = "mem/cache/base.hh" assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") hit_latency = Param.Cycles("The hit latency for this cache") diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index e590410ae..af67f40b6 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -45,6 +45,7 @@ from m5.proxy import * class BasePrefetcher(ClockedObject): type = 'BasePrefetcher' abstract = True + cxx_header = "mem/cache/prefetch/base.hh" size = Param.Int(100, "Number of entries in the hardware prefetch queue") cross_pages = Param.Bool(False, @@ -63,14 +64,17 @@ class BasePrefetcher(ClockedObject): class GHBPrefetcher(BasePrefetcher): type = 'GHBPrefetcher' cxx_class = 'GHBPrefetcher' + cxx_header = "mem/cache/prefetch/ghb.hh" class StridePrefetcher(BasePrefetcher): type = 'StridePrefetcher' cxx_class = 'StridePrefetcher' + cxx_header = "mem/cache/prefetch/stride.hh" class TaggedPrefetcher(BasePrefetcher): type = 'TaggedPrefetcher' cxx_class = 'TaggedPrefetcher' + cxx_header = "mem/cache/prefetch/tagged.hh" diff --git a/src/mem/cache/tags/iic_repl/Repl.py b/src/mem/cache/tags/iic_repl/Repl.py index 4c333e897..577eb8fed 100644 --- a/src/mem/cache/tags/iic_repl/Repl.py +++ b/src/mem/cache/tags/iic_repl/Repl.py @@ -31,9 +31,11 @@ from m5.params import * class Repl(SimObject): type = 'Repl' abstract = True + cxx_header = "mem/cache/tags/iic_repl/repl.hh" class GenRepl(Repl): type = 'GenRepl' + cxx_header = "mem/cache/tags/iic_repl/gen.hh" fresh_res = Param.Int("Fresh pool residency time") num_pools = Param.Int("Number of priority pools") pool_res = Param.Int("Pool residency time") -- cgit v1.2.3