From c58cb8c9dbeef377da180f1fdaaa1c0eadf85550 Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Fri, 7 Jul 2017 14:13:11 +0100 Subject: cpu,mem: Add support for partial loads/stores and wide mem. accesses This changeset adds support for partial (or masked) loads/stores, i.e. loads/stores that can disable accesses to individual bytes within the target address range. In addition, this changeset extends the code to crack memory accesses across most CPU models (TimingSimpleCPU still TBD), so that arbitrarily wide memory accesses are supported. These changes are required for supporting ISAs with wide vectors. Additional authors: - Gabor Dozsa - Tiago Muck Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518 Tested-by: kokoro Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- src/mem/cache/cache.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mem/cache') diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 494a998a5..b72ff4261 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -297,7 +297,8 @@ Cache::promoteWholeLineWrites(PacketPtr pkt) { // Cache line clearing instructions if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && - (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { + (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0) && + !pkt->isMaskedWrite()) { pkt->cmd = MemCmd::WriteLineReq; DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); } -- cgit v1.2.3