From d4273cc9a6f3c00566e97ebcd71509ed14477b37 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 18 Jul 2013 08:31:16 -0400 Subject: mem: Set the cache line size on a system level This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly. --- src/mem/cache/BaseCache.py | 1 - src/mem/cache/base.cc | 4 ++-- src/mem/cache/cache.hh | 6 ------ src/mem/cache/tags/Tags.py | 4 ++-- 4 files changed, 4 insertions(+), 11 deletions(-) (limited to 'src/mem/cache') diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 7f2c1cc6f..df4602199 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -48,7 +48,6 @@ class BaseCache(MemObject): type = 'BaseCache' cxx_header = "mem/cache/base.hh" assoc = Param.Int("associativity") - block_size = Param.Int("block size in bytes") hit_latency = Param.Cycles("The hit latency for this cache") response_latency = Param.Cycles( "Additional cache latency for the return path to core on a miss"); diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 62f1bb21b..03b4d5dc1 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -71,7 +71,7 @@ BaseCache::BaseCache(const Params *p) mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, MSHRQueue_WriteBuffer), - blkSize(p->block_size), + blkSize(p->system->cacheLineSize()), hitLatency(p->hit_latency), responseLatency(p->response_latency), numTarget(p->tgts_per_mshr), @@ -773,7 +773,7 @@ BaseCache::drain(DrainManager *dm) BaseCache * BaseCacheParams::create() { - unsigned numSets = size / (assoc * block_size); + unsigned numSets = size / (assoc * system->cacheLineSize()); assert(tags); diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 729e1f32c..ab884372c 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -99,9 +99,6 @@ class Cache : public BaseCache virtual void recvFunctional(PacketPtr pkt); - virtual unsigned deviceBlockSize() const - { return cache->getBlockSize(); } - virtual AddrRangeList getAddrRanges() const; public: @@ -163,9 +160,6 @@ class Cache : public BaseCache virtual void recvFunctionalSnoop(PacketPtr pkt); - virtual unsigned deviceBlockSize() const - { return cache->getBlockSize(); } - public: MemSidePort(const std::string &_name, Cache *_cache, diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py index c1aad2444..c5beff4a7 100644 --- a/src/mem/cache/tags/Tags.py +++ b/src/mem/cache/tags/Tags.py @@ -46,8 +46,8 @@ class BaseTags(ClockedObject): # Get the size from the parent (cache) size = Param.MemorySize(Parent.size, "capacity in bytes") - # Get the block size from the parent (cache) - block_size = Param.Int(Parent.block_size, "block size in bytes") + # Get the block size from the parent (system) + block_size = Param.Int(Parent.cache_line_size, "block size in bytes") # Get the hit latency from the parent (cache) hit_latency = Param.Cycles(Parent.hit_latency, -- cgit v1.2.3