From d5ac1cb51f2e08531794e1dcbb17e47f51041c4f Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Tue, 15 Aug 2006 16:21:46 -0400 Subject: Pulled out changes to fix EIO programs with caches. Also fixes any translatingPort read/write Blob function problems with caches. -Basically removed the ASID from places it is no longer needed due to PageTable src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/prefetch/base_prefetcher.hh: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: Remove asid where it wasn't neccesary anymore due to Page Table --HG-- extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28 --- src/mem/cache/cache.hh | 4 +-- src/mem/cache/cache_impl.hh | 36 +++++++++++------------ src/mem/cache/miss/blocking_buffer.cc | 6 ++-- src/mem/cache/miss/blocking_buffer.hh | 10 +++---- src/mem/cache/miss/miss_queue.cc | 22 +++++++------- src/mem/cache/miss/miss_queue.hh | 10 +++---- src/mem/cache/miss/mshr.cc | 7 ++--- src/mem/cache/miss/mshr.hh | 2 +- src/mem/cache/miss/mshr_queue.cc | 14 ++++----- src/mem/cache/miss/mshr_queue.hh | 8 +++--- src/mem/cache/prefetch/base_prefetcher.cc | 2 +- src/mem/cache/prefetch/base_prefetcher.hh | 2 +- src/mem/cache/tags/fa_lru.cc | 8 +++--- src/mem/cache/tags/fa_lru.hh | 10 +++---- src/mem/cache/tags/iic.cc | 43 +++++++++++++-------------- src/mem/cache/tags/iic.hh | 14 ++++----- src/mem/cache/tags/lru.cc | 29 +++++++++---------- src/mem/cache/tags/lru.hh | 12 ++++---- src/mem/cache/tags/split.cc | 48 +++++++++++++++---------------- src/mem/cache/tags/split.hh | 10 +++---- src/mem/cache/tags/split_lifo.cc | 29 +++++++++---------- src/mem/cache/tags/split_lifo.hh | 12 ++++---- src/mem/cache/tags/split_lru.cc | 30 +++++++++---------- src/mem/cache/tags/split_lru.hh | 12 ++++---- 24 files changed, 183 insertions(+), 197 deletions(-) (limited to 'src/mem/cache') diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index a26d91709..989b8743e 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -108,7 +108,7 @@ class Cache : public BaseCache * Temporarily move a block into a MSHR. * @todo Remove this when LSQ/SB are fixed and implemented in memtest. */ - void pseudoFill(Addr addr, int asid); + void pseudoFill(Addr addr); /** * Temporarily move a block into an existing MSHR. @@ -218,7 +218,7 @@ class Cache : public BaseCache * @param asid The address space ID of the address. * @todo Is this function necessary? */ - void invalidateBlk(Addr addr, int asid); + void invalidateBlk(Addr addr); /** * Squash all requests associated with specified thread. diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index b215960c4..2f9415852 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -184,8 +184,8 @@ Cache::access(PacketPtr &pkt) && !pkt->isWrite()) { //Upgrade or Invalidate //Look into what happens if two slave caches on bus - DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(), - pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1), + DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(), + pkt->getAddr() & (((ULL(1))<<48)-1), pkt->getAddr() & ~((Addr)blkSize - 1)); //@todo Should this return latency have the hit latency in it? @@ -205,7 +205,7 @@ Cache::access(PacketPtr &pkt) if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() && (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) { // not outstanding misses, can do this - MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr(), pkt->req->getAsid()); + MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr()); if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) { if (outstanding_miss) { warn("WriteInv doing a fastallocate" @@ -220,8 +220,8 @@ Cache::access(PacketPtr &pkt) missQueue->doWriteback(writebacks.front()); writebacks.pop_front(); } - DPRINTF(Cache, "%s %d %x %s blk_addr: %x pc %x\n", pkt->cmdString(), - pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss", + DPRINTF(Cache, "%s %x %s blk_addr: %x pc %x\n", pkt->cmdString(), + pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss", pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC()); if (blk) { // Hit @@ -311,10 +311,10 @@ Cache::handleResponse(Packet * &pkt) template void -Cache::pseudoFill(Addr addr, int asid) +Cache::pseudoFill(Addr addr) { // Need to temporarily move this blk into MSHRs - MSHR *mshr = missQueue->allocateTargetList(addr, asid); + MSHR *mshr = missQueue->allocateTargetList(addr); int lat; PacketList dummy; // Read the data into the mshr @@ -324,7 +324,7 @@ Cache::pseudoFill(Addr addr, int asid) // can overload order since it isn't used on non pending blocks mshr->order = blk->status; // temporarily remove the block from the cache. - tags->invalidateBlk(addr, asid); + tags->invalidateBlk(addr); } template @@ -342,7 +342,7 @@ Cache::pseudoFill(MSHR *mshr) // can overload order since it isn't used on non pending blocks mshr->order = blk->status; // temporarily remove the block from the cache. - tags->invalidateBlk(mshr->pkt->getAddr(), mshr->pkt->req->getAsid()); + tags->invalidateBlk(mshr->pkt->getAddr()); } @@ -361,7 +361,7 @@ Cache::snoop(Packet * &pkt) Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt); - MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid()); + MSHR *mshr = missQueue->findMSHR(blk_addr); if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req //If we find an mshr, and it is in service, we need to NACK or invalidate if (mshr) { @@ -395,7 +395,7 @@ Cache::snoop(Packet * &pkt) } //We also need to check the writeback buffers and handle those std::vector writebacks; - if (missQueue->findWrites(blk_addr, pkt->req->getAsid(), writebacks)) { + if (missQueue->findWrites(blk_addr, writebacks)) { DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1)); //Look through writebacks for any non-uncachable writes, use that @@ -461,9 +461,9 @@ Cache::snoopResponse(Packet * &pkt) template void -Cache::invalidateBlk(Addr addr, int asid) +Cache::invalidateBlk(Addr addr) { - tags->invalidateBlk(addr,asid); + tags->invalidateBlk(addr); } @@ -479,8 +479,8 @@ Cache::probe(Packet * &pkt, bool update) if (pkt->isInvalidate() && !pkt->isRead() && !pkt->isWrite()) { //Upgrade or Invalidate, satisfy it, don't forward - DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(), - pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1), + DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(), + pkt->getAddr() & (((ULL(1))<<48)-1), pkt->getAddr() & ~((Addr)blkSize - 1)); pkt->flags |= SATISFIED; return 0; @@ -496,11 +496,11 @@ Cache::probe(Packet * &pkt, bool update) Addr blk_addr = pkt->getAddr() & ~(blkSize - 1); // There can only be one matching outstanding miss. - MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid()); + MSHR* mshr = missQueue->findMSHR(blk_addr); // There can be many matching outstanding writes. std::vector writes; - missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes); + missQueue->findWrites(blk_addr, writes); if (!update) { memSidePort->sendFunctional(pkt); @@ -645,7 +645,7 @@ Cache::snoopProbe(PacketPtr &pkt, bool update) { Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt); - MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid()); + MSHR *mshr = missQueue->findMSHR(blk_addr); CacheBlk::State new_state = 0; bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); if (satisfy) { diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index 2f61e8a54..67fc7ae56 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -76,7 +76,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) if (!pkt->needsResponse()) { wb.allocateAsBuffer(pkt); } else { - wb.allocate(pkt->cmd, blk_addr, pkt->req->getAsid(), blk_size, pkt); + wb.allocate(pkt->cmd, blk_addr, blk_size, pkt); } memcpy(wb.pkt->getPtr(), pkt->getPtr(), blk_size); @@ -89,7 +89,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) if (!pkt->needsResponse()) { miss.allocateAsBuffer(pkt); } else { - miss.allocate(pkt->cmd, blk_addr, pkt->req->getAsid(), blk_size, pkt); + miss.allocate(pkt->cmd, blk_addr, blk_size, pkt); } if (!pkt->req->isUncacheable()) { miss.pkt->flags |= CACHE_LINE_FILL; @@ -202,7 +202,7 @@ BlockingBuffer::squash(int threadNum) } void -BlockingBuffer::doWriteback(Addr addr, int asid, +BlockingBuffer::doWriteback(Addr addr, int size, uint8_t *data, bool compressed) { // Generate request diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh index a6261f62c..641d5a798 100644 --- a/src/mem/cache/miss/blocking_buffer.hh +++ b/src/mem/cache/miss/blocking_buffer.hh @@ -121,7 +121,7 @@ public: * @param time The time the miss is detected. * @param target The target for the fetch. */ - MSHR* fetchBlock(Addr addr, int asid, int blk_size, Tick time, + MSHR* fetchBlock(Addr addr, int blk_size, Tick time, Packet * &target) { fatal("Unimplemented"); @@ -183,7 +183,7 @@ public: * @param asid The address space id. * @return A pointer to miss if it matches. */ - MSHR* findMSHR(Addr addr, int asid) + MSHR* findMSHR(Addr addr) { if (miss.addr == addr && miss.pkt) return &miss; @@ -197,7 +197,7 @@ public: * @param writes List of pointers to the matching writes. * @return True if there is a matching write. */ - bool findWrites(Addr addr, int asid, std::vector& writes) + bool findWrites(Addr addr, std::vector& writes) { if (wb.addr == addr && wb.pkt) { writes.push_back(&wb); @@ -216,7 +216,7 @@ public: * @param data The data to write, can be NULL. * @param compressed True if the data is compressed. */ - void doWriteback(Addr addr, int asid, + void doWriteback(Addr addr, int size, uint8_t *data, bool compressed); /** @@ -247,7 +247,7 @@ public: /** * Dummy implmentation. */ - MSHR* allocateTargetList(Addr addr, int asid) + MSHR* allocateTargetList(Addr addr) { fatal("Unimplemented"); } diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index 4a3dc1062..76fb25716 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -410,7 +410,7 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1); MSHR* mshr = NULL; if (!pkt->req->isUncacheable()) { - mshr = mq.findMatch(blkAddr, pkt->req->getAsid()); + mshr = mq.findMatch(blkAddr); if (mshr) { //@todo remove hw_pf here mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; @@ -454,12 +454,12 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) } MSHR* -MissQueue::fetchBlock(Addr addr, int asid, int blk_size, Tick time, +MissQueue::fetchBlock(Addr addr, int blk_size, Tick time, Packet * &target) { Addr blkAddr = addr & ~(Addr)(blk_size - 1); - assert(mq.findMatch(addr, asid) == NULL); - MSHR *mshr = mq.allocateFetch(blkAddr, asid, blk_size, target); + assert(mq.findMatch(addr) == NULL); + MSHR *mshr = mq.allocateFetch(blkAddr, blk_size, target); mshr->order = order++; mshr->pkt->flags |= CACHE_LINE_FILL; if (mq.isFull()) { @@ -697,19 +697,19 @@ MissQueue::squash(int threadNum) } MSHR* -MissQueue::findMSHR(Addr addr, int asid) const +MissQueue::findMSHR(Addr addr) const { - return mq.findMatch(addr,asid); + return mq.findMatch(addr); } bool -MissQueue::findWrites(Addr addr, int asid, vector &writes) const +MissQueue::findWrites(Addr addr, vector &writes) const { - return wb.findMatches(addr,asid,writes); + return wb.findMatches(addr,writes); } void -MissQueue::doWriteback(Addr addr, int asid, +MissQueue::doWriteback(Addr addr, int size, uint8_t *data, bool compressed) { // Generate request @@ -740,9 +740,9 @@ MissQueue::doWriteback(Packet * &pkt) MSHR* -MissQueue::allocateTargetList(Addr addr, int asid) +MissQueue::allocateTargetList(Addr addr) { - MSHR* mshr = mq.allocateTargetList(addr, asid, blkSize); + MSHR* mshr = mq.allocateTargetList(addr, blkSize); mshr->pkt->flags |= CACHE_LINE_FILL; if (mq.isFull()) { cache->setBlocked(Blocked_NoMSHRs); diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh index c558df956..505d1f90c 100644 --- a/src/mem/cache/miss/miss_queue.hh +++ b/src/mem/cache/miss/miss_queue.hh @@ -228,7 +228,7 @@ class MissQueue * @param time The time the miss is detected. * @param target The target for the fetch. */ - MSHR* fetchBlock(Addr addr, int asid, int blk_size, Tick time, + MSHR* fetchBlock(Addr addr, int blk_size, Tick time, Packet * &target); /** @@ -289,7 +289,7 @@ class MissQueue * @warning Currently only searches the miss queue. If non write allocate * might need to search the write buffer for coherence. */ - MSHR* findMSHR(Addr addr, int asid) const; + MSHR* findMSHR(Addr addr) const; /** * Searches for the supplied address in the write buffer. @@ -298,7 +298,7 @@ class MissQueue * @param writes The list of writes that match the address. * @return True if any writes are found */ - bool findWrites(Addr addr, int asid, std::vector& writes) const; + bool findWrites(Addr addr, std::vector& writes) const; /** * Perform a writeback of dirty data to the given address. @@ -309,7 +309,7 @@ class MissQueue * @param data The data to write, can be NULL. * @param compressed True if the data is compressed. */ - void doWriteback(Addr addr, int asid, + void doWriteback(Addr addr, int size, uint8_t *data, bool compressed); /** @@ -342,7 +342,7 @@ class MissQueue * @param asid The address space ID. * @return A pointer to the allocated MSHR. */ - MSHR* allocateTargetList(Addr addr, int asid); + MSHR* allocateTargetList(Addr addr); }; diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index db2f40c56..64bcbb833 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -54,7 +54,7 @@ MSHR::MSHR() } void -MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size, +MSHR::allocate(Packet::Command cmd, Addr _addr, int size, Packet * &target) { addr = _addr; @@ -88,7 +88,6 @@ void MSHR::allocateAsBuffer(Packet * &target) { addr = target->getAddr(); - asid = target->req->getAsid(); threadNum = target->req->getThreadNum(); pkt = new Packet(target->req, target->cmd, -1); pkt->allocate(); @@ -159,9 +158,9 @@ MSHR::dump() { ccprintf(cerr, "inService: %d thread: %d\n" - "Addr: %x asid: %d ntargets %d\n" + "Addr: %x ntargets %d\n" "Targets:\n", - inService, threadNum, addr, asid, ntargets); + inService, threadNum, addr, ntargets); TargetListIterator tar_it = targets.begin(); for (int i = 0; i < ntargets; i++) { diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh index ad2865973..028259b35 100644 --- a/src/mem/cache/miss/mshr.hh +++ b/src/mem/cache/miss/mshr.hh @@ -100,7 +100,7 @@ public: * @param size The number of bytes to pktuest. * @param pkt The original miss. */ - void allocate(Packet::Command cmd, Addr addr, int asid, int size, + void allocate(Packet::Command cmd, Addr addr, int size, Packet * &pkt); /** diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index 6516a99f8..f13f48dec 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -55,7 +55,7 @@ MSHRQueue::~MSHRQueue() } MSHR* -MSHRQueue::findMatch(Addr addr, int asid) const +MSHRQueue::findMatch(Addr addr) const { MSHR::ConstIterator i = allocatedList.begin(); MSHR::ConstIterator end = allocatedList.end(); @@ -69,7 +69,7 @@ MSHRQueue::findMatch(Addr addr, int asid) const } bool -MSHRQueue::findMatches(Addr addr, int asid, vector& matches) const +MSHRQueue::findMatches(Addr addr, vector& matches) const { // Need an empty vector assert(matches.empty()); @@ -136,7 +136,7 @@ MSHRQueue::allocate(Packet * &pkt, int size) mshr->allocateAsBuffer(pkt); } else { assert(size !=0); - mshr->allocate(pkt->cmd, aligned_addr, pkt->req->getAsid(), size, pkt); + mshr->allocate(pkt->cmd, aligned_addr, size, pkt); allocatedTargets += 1; } mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); @@ -147,12 +147,12 @@ MSHRQueue::allocate(Packet * &pkt, int size) } MSHR* -MSHRQueue::allocateFetch(Addr addr, int asid, int size, Packet * &target) +MSHRQueue::allocateFetch(Addr addr, int size, Packet * &target) { MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); - mshr->allocate(Packet::ReadReq, addr, asid, size, target); + mshr->allocate(Packet::ReadReq, addr, size, target); mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); mshr->readyIter = pendingList.insert(pendingList.end(), mshr); @@ -161,13 +161,13 @@ MSHRQueue::allocateFetch(Addr addr, int asid, int size, Packet * &target) } MSHR* -MSHRQueue::allocateTargetList(Addr addr, int asid, int size) +MSHRQueue::allocateTargetList(Addr addr, int size) { MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); Packet * dummy; - mshr->allocate(Packet::ReadReq, addr, asid, size, dummy); + mshr->allocate(Packet::ReadReq, addr, size, dummy); mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); mshr->inService = true; ++inServiceMSHRs; diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh index 02b6a026d..ea5f101b7 100644 --- a/src/mem/cache/miss/mshr_queue.hh +++ b/src/mem/cache/miss/mshr_queue.hh @@ -90,7 +90,7 @@ class MSHRQueue { * @param asid The address space id. * @return Pointer to the matching MSHR, null if not found. */ - MSHR* findMatch(Addr addr, int asid) const; + MSHR* findMatch(Addr addr) const; /** * Find and return all the matching MSHRs in the provided vector. @@ -100,7 +100,7 @@ class MSHRQueue { * @return True if any matches are found, false otherwise. * @todo Typedef the vector?? */ - bool findMatches(Addr addr, int asid, std::vector& matches) const; + bool findMatches(Addr addr, std::vector& matches) const; /** * Find any pending pktuests that overlap the given request. @@ -129,7 +129,7 @@ class MSHRQueue { * @param target The first target for the pktuest. * @return Pointer to the new MSHR. */ - MSHR* allocateFetch(Addr addr, int asid, int size, Packet * &target); + MSHR* allocateFetch(Addr addr, int size, Packet * &target); /** * Allocate a target list for the given address. @@ -138,7 +138,7 @@ class MSHRQueue { * @param size The number of bytes to pktuest. * @return Pointer to the new MSHR. */ - MSHR* allocateTargetList(Addr addr, int asid, int size); + MSHR* allocateTargetList(Addr addr, int size); /** * Removes the given MSHR from the queue. This places the MSHR on the diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc index 897551989..5e50c48bd 100644 --- a/src/mem/cache/prefetch/base_prefetcher.cc +++ b/src/mem/cache/prefetch/base_prefetcher.cc @@ -198,7 +198,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time) } //Check if it is already in the miss_queue - if (inMissQueue(prefetch->getAddr(), prefetch->req->getAsid())) { + if (inMissQueue(prefetch->getAddr())) { addr++; delay++; continue; diff --git a/src/mem/cache/prefetch/base_prefetcher.hh b/src/mem/cache/prefetch/base_prefetcher.hh index 3e4fc89d1..d7ea41961 100644 --- a/src/mem/cache/prefetch/base_prefetcher.hh +++ b/src/mem/cache/prefetch/base_prefetcher.hh @@ -108,7 +108,7 @@ class BasePrefetcher virtual bool inCache(Packet * &pkt) = 0; - virtual bool inMissQueue(Addr address, int asid) = 0; + virtual bool inMissQueue(Addr address) = 0; std::list::iterator inPrefetch(Addr address); }; diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index 82d2c410d..784ba1311 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -145,7 +145,7 @@ FALRU::hashLookup(Addr addr) const } bool -FALRU::probe(int asid, Addr addr) const +FALRU::probe(Addr addr) const { Addr blkAddr = blkAlign(addr); FALRUBlk* blk = hashLookup(blkAddr); @@ -153,7 +153,7 @@ FALRU::probe(int asid, Addr addr) const } void -FALRU::invalidateBlk(int asid, Addr addr) +FALRU::invalidateBlk(Addr addr) { Addr blkAddr = blkAlign(addr); FALRUBlk* blk = (*tagHash.find(blkAddr)).second; @@ -166,7 +166,7 @@ FALRU::invalidateBlk(int asid, Addr addr) } FALRUBlk* -FALRU::findBlock(Addr addr, int asid, int &lat, int *inCache) +FALRU::findBlock(Addr addr, int &lat, int *inCache) { accesses++; int tmp_in_cache = 0; @@ -242,7 +242,7 @@ FALRU::findBlock(Packet * &pkt, int &lat, int *inCache) } FALRUBlk* -FALRU::findBlock(Addr addr, int asid) const +FALRU::findBlock(Addr addr) const { Addr blkAddr = blkAlign(addr); FALRUBlk* blk = hashLookup(blkAddr); diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 444954917..f9d4d7109 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -170,14 +170,14 @@ public: * @param addr The address to look for. * @return True if the address is in the cache. */ - bool probe(int asid, Addr addr) const; + bool probe(Addr addr) const; /** * Invalidate the cache block that contains the given addr. * @param asid The address space ID. * @param addr The address to invalidate. */ - void invalidateBlk(int asid, Addr addr); + void invalidateBlk(Addr addr); /** * Find the block in the cache and update the replacement data. Returns @@ -188,7 +188,7 @@ public: * @param inCache The FALRUBlk::inCache flags. * @return Pointer to the cache block. */ - FALRUBlk* findBlock(Addr addr, int asid, int &lat, int *inCache = 0); + FALRUBlk* findBlock(Addr addr, int &lat, int *inCache = 0); /** * Find the block in the cache and update the replacement data. Returns @@ -206,7 +206,7 @@ public: * @param asid The address space ID. * @return Pointer to the cache block. */ - FALRUBlk* findBlock(Addr addr, int asid) const; + FALRUBlk* findBlock(Addr addr) const; /** * Find a replacement block for the address provided. @@ -330,7 +330,7 @@ public: * @param asid The address space ID. * @param writebacks List for any generated writeback pktuests. */ - void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) + void doCopy(Addr source, Addr dest, PacketList &writebacks) { } diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index 847fabc88..1377c8613 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -221,13 +221,13 @@ IIC::regStats(const string &name) // probe cache for presence of given block. bool -IIC::probe(int asid, Addr addr) const +IIC::probe(Addr addr) const { - return (findBlock(addr,asid) != NULL); + return (findBlock(addr) != NULL); } IICTag* -IIC::findBlock(Addr addr, int asid, int &lat) +IIC::findBlock(Addr addr, int &lat) { Addr tag = extractTag(addr); unsigned set = hash(addr); @@ -238,11 +238,11 @@ IIC::findBlock(Addr addr, int asid, int &lat) if (PROFILE_IIC) setAccess.sample(set); - IICTag *tag_ptr = sets[set].findTag(asid, tag, chain_ptr); + IICTag *tag_ptr = sets[set].findTag(tag, chain_ptr); set_lat = 1; if (tag_ptr == NULL && chain_ptr != tagNull) { int secondary_depth; - tag_ptr = secondaryChain(asid, tag, chain_ptr, &secondary_depth); + tag_ptr = secondaryChain(tag, chain_ptr, &secondary_depth); set_lat += secondary_depth; // set depth for statistics fix this later!!! egh sets[set].depth = set_lat; @@ -252,7 +252,7 @@ IIC::findBlock(Addr addr, int asid, int &lat) // need to preserve chain: fix this egh sets[set].tags[assoc-1]->chain_ptr = tag_ptr->chain_ptr; tagSwap(tag_ptr - tagStore, sets[set].tags[assoc-1] - tagStore); - tag_ptr = sets[set].findTag(asid, tag, chain_ptr); + tag_ptr = sets[set].findTag(tag, chain_ptr); assert(tag_ptr!=NULL); } @@ -288,7 +288,6 @@ IICTag* IIC::findBlock(Packet * &pkt, int &lat) { Addr addr = pkt->getAddr(); - int asid = pkt->req->getAsid(); Addr tag = extractTag(addr); unsigned set = hash(addr); @@ -299,11 +298,11 @@ IIC::findBlock(Packet * &pkt, int &lat) if (PROFILE_IIC) setAccess.sample(set); - IICTag *tag_ptr = sets[set].findTag(asid, tag, chain_ptr); + IICTag *tag_ptr = sets[set].findTag(tag, chain_ptr); set_lat = 1; if (tag_ptr == NULL && chain_ptr != tagNull) { int secondary_depth; - tag_ptr = secondaryChain(asid, tag, chain_ptr, &secondary_depth); + tag_ptr = secondaryChain(tag, chain_ptr, &secondary_depth); set_lat += secondary_depth; // set depth for statistics fix this later!!! egh sets[set].depth = set_lat; @@ -313,7 +312,7 @@ IIC::findBlock(Packet * &pkt, int &lat) // need to preserve chain: fix this egh sets[set].tags[assoc-1]->chain_ptr = tag_ptr->chain_ptr; tagSwap(tag_ptr - tagStore, sets[set].tags[assoc-1] - tagStore); - tag_ptr = sets[set].findTag(asid, tag, chain_ptr); + tag_ptr = sets[set].findTag(tag, chain_ptr); assert(tag_ptr!=NULL); } @@ -346,17 +345,17 @@ IIC::findBlock(Packet * &pkt, int &lat) } IICTag* -IIC::findBlock(Addr addr, int asid) const +IIC::findBlock(Addr addr) const { Addr tag = extractTag(addr); unsigned set = hash(addr); unsigned long chain_ptr; - IICTag *tag_ptr = sets[set].findTag(asid, tag, chain_ptr); + IICTag *tag_ptr = sets[set].findTag(tag, chain_ptr); if (tag_ptr == NULL && chain_ptr != tagNull) { int secondary_depth; - tag_ptr = secondaryChain(asid, tag, chain_ptr, &secondary_depth); + tag_ptr = secondaryChain(tag, chain_ptr, &secondary_depth); } return tag_ptr; } @@ -658,7 +657,7 @@ IIC::tagSwap(unsigned long index1, unsigned long index2) IICTag * -IIC::secondaryChain(int asid, Addr tag, unsigned long chain_ptr, +IIC::secondaryChain(Addr tag, unsigned long chain_ptr, int *_depth) const { int depth = 0; @@ -666,7 +665,6 @@ IIC::secondaryChain(int asid, Addr tag, unsigned long chain_ptr, DPRINTF(IIC,"Searching secondary at %d for %x\n", chain_ptr, tag<numData; ++i) { dataReferenceCount[tag_ptr->data_ptr[i]]--; @@ -781,11 +779,11 @@ IIC::writeData(IICTag *blk, uint8_t *write_data, int size, * @todo This code can break if the src is evicted to get a tag for the dest. */ void -IIC::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) +IIC::doCopy(Addr source, Addr dest, PacketList &writebacks) { //Copy unsuported now #if 0 - IICTag *dest_tag = findBlock(dest, asid); + IICTag *dest_tag = findBlock(dest); if (dest_tag) { for (int i = 0; i < dest_tag->numData; ++i) { @@ -799,12 +797,11 @@ IIC::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) dest_tag->re = (void*) repl->add(dest_tag - tagStore); dest_tag->set = hash(dest); dest_tag->tag = extractTag(dest); - dest_tag->asid = asid; dest_tag->status = BlkValid | BlkWritable; } // Find the source tag here since it might move if we need to find a // tag for the destination. - IICTag *src_tag = findBlock(source, asid); + IICTag *src_tag = findBlock(source); assert(src_tag); assert(!cache->doData() || src_tag->size <= trivialSize || src_tag->numData > 0); @@ -841,7 +838,7 @@ IIC::fixCopy(Packet * &pkt, PacketList &writebacks) // if reference counter is greater than 1, do copy // else do write Addr blk_addr = blkAlign(pkt->getAddr); - IICTag* blk = findBlock(blk_addr, pkt->req->getAsid()); + IICTag* blk = findBlock(blk_addr); if (blk->numData > 0 && dataReferenceCount[blk->data_ptr[0]] != 1) { // copy the data @@ -853,7 +850,7 @@ IIC::fixCopy(Packet * &pkt, PacketList &writebacks) /** * @todo Remove this refetch once we change IIC to pointer based */ - blk = findBlock(blk_addr, pkt->req->getAsid()); + blk = findBlock(blk_addr); assert(blk); if (cache->doData()) { memcpy(&(dataBlks[new_data][0]), diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 514d16bdd..2357bdce3 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -117,7 +117,7 @@ class IICSet{ * @param chain_ptr The chain pointer to start the search of the secondary * @return Pointer to the tag, NULL if not found. */ - IICTag* findTag(int asid, Addr tag, unsigned long &chain_ptr) + IICTag* findTag( Addr tag, unsigned long &chain_ptr) { depth = 1; for (int i = 0; i < assoc; ++i) { @@ -401,7 +401,7 @@ class IIC : public BaseTags * @param addr The address to find. * @return true if it is found. */ - bool probe(int asid, Addr addr) const; + bool probe(Addr addr) const; /** * Swap the position of two tags. @@ -439,7 +439,7 @@ class IIC : public BaseTags * @param asid The address space ID. * @param addr The address to invalidate. */ - void invalidateBlk(int asid, Addr addr); + void invalidateBlk(Addr addr); /** * Find the block and update the replacement data. This call also returns @@ -449,7 +449,7 @@ class IIC : public BaseTags * @param lat The access latency. * @return A pointer to the block found, if any. */ - IICTag* findBlock(Addr addr, int asid, int &lat); + IICTag* findBlock(Addr addr, int &lat); /** * Find the block and update the replacement data. This call also returns @@ -466,7 +466,7 @@ class IIC : public BaseTags * @param asid The address space ID. * @return A pointer to the block found, if any. */ - IICTag* findBlock(Addr addr, int asid) const; + IICTag* findBlock(Addr addr) const; /** * Find a replacement block for the address provided. @@ -504,7 +504,7 @@ class IIC : public BaseTags * @param asid The address space DI. * @param writebacks List for any generated writeback pktuests. */ - void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks); + void doCopy(Addr source, Addr dest, PacketList &writebacks); /** * If a block is currently marked copy on write, copy it before writing. @@ -534,7 +534,7 @@ private: * @param depth The number of hash lookups made while searching. * @return A pointer to the block if found. */ - IICTag *secondaryChain(int asid, Addr tag, unsigned long chain_ptr, + IICTag *secondaryChain(Addr tag, unsigned long chain_ptr, int *depth) const; /** diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 556025a3a..976bbeff2 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -43,7 +43,7 @@ using namespace std; LRUBlk* -CacheSet::findBlk(int asid, Addr tag) const +CacheSet::findBlk(Addr tag) const { for (int i = 0; i < assoc; ++i) { if (blks[i]->tag == tag && blks[i]->isValid()) { @@ -135,7 +135,6 @@ LRU::LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency) : // table; won't matter because the block is invalid blk->tag = j; blk->whenReady = 0; - blk->asid = -1; blk->isTouched = false; blk->size = blkSize; sets[i].blks[j]=blk; @@ -153,23 +152,23 @@ LRU::~LRU() // probe cache for presence of given block. bool -LRU::probe(int asid, Addr addr) const +LRU::probe(Addr addr) const { // return(findBlock(Read, addr, asid) != 0); Addr tag = extractTag(addr); unsigned myset = extractSet(addr); - LRUBlk *blk = sets[myset].findBlk(asid, tag); + LRUBlk *blk = sets[myset].findBlk(tag); return (blk != NULL); // true if in cache } LRUBlk* -LRU::findBlock(Addr addr, int asid, int &lat) +LRU::findBlock(Addr addr, int &lat) { Addr tag = extractTag(addr); unsigned set = extractSet(addr); - LRUBlk *blk = sets[set].findBlk(asid, tag); + LRUBlk *blk = sets[set].findBlk(tag); lat = hitLatency; if (blk != NULL) { // move this block to head of the MRU list @@ -188,11 +187,10 @@ LRUBlk* LRU::findBlock(Packet * &pkt, int &lat) { Addr addr = pkt->getAddr(); - int asid = 0;//pkt->req->getAsid(); Addr tag = extractTag(addr); unsigned set = extractSet(addr); - LRUBlk *blk = sets[set].findBlk(asid, tag); + LRUBlk *blk = sets[set].findBlk(tag); lat = hitLatency; if (blk != NULL) { // move this block to head of the MRU list @@ -208,11 +206,11 @@ LRU::findBlock(Packet * &pkt, int &lat) } LRUBlk* -LRU::findBlock(Addr addr, int asid) const +LRU::findBlock(Addr addr) const { Addr tag = extractTag(addr); unsigned set = extractSet(addr); - LRUBlk *blk = sets[set].findBlk(asid, tag); + LRUBlk *blk = sets[set].findBlk(tag); return blk; } @@ -242,9 +240,9 @@ LRU::findReplacement(Packet * &pkt, PacketList &writebacks, } void -LRU::invalidateBlk(int asid, Addr addr) +LRU::invalidateBlk(Addr addr) { - LRUBlk *blk = findBlock(addr, asid); + LRUBlk *blk = findBlock(addr); if (blk) { blk->status = 0; blk->isTouched = false; @@ -253,13 +251,13 @@ LRU::invalidateBlk(int asid, Addr addr) } void -LRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) +LRU::doCopy(Addr source, Addr dest, PacketList &writebacks) { assert(source == blkAlign(source)); assert(dest == blkAlign(dest)); - LRUBlk *source_blk = findBlock(source, asid); + LRUBlk *source_blk = findBlock(source); assert(source_blk); - LRUBlk *dest_blk = findBlock(dest, asid); + LRUBlk *dest_blk = findBlock(dest); if (dest_blk == NULL) { // Need to do a replacement Request *search = new Request(dest,1,0); @@ -285,7 +283,6 @@ LRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) writebacks.push_back(writeback); } dest_blk->tag = extractTag(dest); - dest_blk->asid = asid; delete search; delete pkt; } diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh index 8f0f3ae27..a3a56a0e6 100644 --- a/src/mem/cache/tags/lru.hh +++ b/src/mem/cache/tags/lru.hh @@ -72,7 +72,7 @@ class CacheSet * @param tag The Tag to find. * @return Pointer to the block if found. */ - LRUBlk* findBlk(int asid, Addr tag) const; + LRUBlk* findBlk(Addr tag) const; /** * Move the given block to the head of the list. @@ -158,14 +158,14 @@ public: * @param addr The address to find. * @return True if the address is in the cache. */ - bool probe(int asid, Addr addr) const; + bool probe(Addr addr) const; /** * Invalidate the block containing the given address. * @param asid The address space ID. * @param addr The address to invalidate. */ - void invalidateBlk(int asid, Addr addr); + void invalidateBlk(Addr addr); /** * Finds the given address in the cache and update replacement data. @@ -184,7 +184,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - LRUBlk* findBlock(Addr addr, int asid, int &lat); + LRUBlk* findBlock(Addr addr, int &lat); /** * Finds the given address in the cache, do not update replacement data. @@ -192,7 +192,7 @@ public: * @param asid The address space ID. * @return Pointer to the cache block if found. */ - LRUBlk* findBlock(Addr addr, int asid) const; + LRUBlk* findBlock(Addr addr) const; /** * Find a replacement block for the address provided. @@ -309,7 +309,7 @@ public: * @param asid The address space DI. * @param writebacks List for any generated writeback pktuests. */ - void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks); + void doCopy(Addr source, Addr dest, PacketList &writebacks); /** * No impl. diff --git a/src/mem/cache/tags/split.cc b/src/mem/cache/tags/split.cc index bf23fb8cb..690eea22e 100644 --- a/src/mem/cache/tags/split.cc +++ b/src/mem/cache/tags/split.cc @@ -253,14 +253,14 @@ Split::regStats(const string &name) // probe cache for presence of given block. bool -Split::probe(int asid, Addr addr) const +Split::probe(Addr addr) const { - bool success = lru->probe(asid, addr); + bool success = lru->probe(addr); if (!success) { if (lifo && lifo_net) - success = lifo_net->probe(asid, addr); + success = lifo_net->probe(addr); else if (lru_net) - success = lru_net->probe(asid, addr); + success = lru_net->probe(addr); } return success; @@ -278,7 +278,7 @@ Split::findBlock(Packet * &pkt, int &lat) memHash[aligned] = 1; } - SplitBlk *blk = lru->findBlock(pkt->getAddr(), pkt->req->getAsid(), lat); + SplitBlk *blk = lru->findBlock(pkt->getAddr(), lat); if (blk) { if (pkt->nic_pkt()) { NR_CP_hits++; @@ -287,10 +287,10 @@ Split::findBlock(Packet * &pkt, int &lat) } } else { if (lifo && lifo_net) { - blk = lifo_net->findBlock(pkt->getAddr(), pkt->req->getAsid(), lat); + blk = lifo_net->findBlock(pkt->getAddr(), lat); } else if (lru_net) { - blk = lru_net->findBlock(pkt->getAddr(), pkt->req->getAsid(), lat); + blk = lru_net->findBlock(pkt->getAddr(), lat); } if (blk) { if (pkt->nic_pkt()) { @@ -320,14 +320,14 @@ Split::findBlock(Packet * &pkt, int &lat) } SplitBlk* -Split::findBlock(Addr addr, int asid, int &lat) +Split::findBlock(Addr addr, int &lat) { - SplitBlk *blk = lru->findBlock(addr, asid, lat); + SplitBlk *blk = lru->findBlock(addr, lat); if (!blk) { if (lifo && lifo_net) { - blk = lifo_net->findBlock(addr, asid, lat); + blk = lifo_net->findBlock(addr, lat); } else if (lru_net) { - blk = lru_net->findBlock(addr, asid, lat); + blk = lru_net->findBlock(addr, lat); } } @@ -335,14 +335,14 @@ Split::findBlock(Addr addr, int asid, int &lat) } SplitBlk* -Split::findBlock(Addr addr, int asid) const +Split::findBlock(Addr addr) const { - SplitBlk *blk = lru->findBlock(addr, asid); + SplitBlk *blk = lru->findBlock(addr); if (!blk) { if (lifo && lifo_net) { - blk = lifo_net->findBlock(addr, asid); + blk = lifo_net->findBlock(addr); } else if (lru_net) { - blk = lru_net->findBlock(addr, asid); + blk = lru_net->findBlock(addr); } } @@ -403,14 +403,14 @@ Split::findReplacement(Packet * &pkt, PacketList &writebacks, } void -Split::invalidateBlk(int asid, Addr addr) +Split::invalidateBlk(Addr addr) { - SplitBlk *blk = lru->findBlock(addr, asid); + SplitBlk *blk = lru->findBlock(addr); if (!blk) { if (lifo && lifo_net) - blk = lifo_net->findBlock(addr, asid); + blk = lifo_net->findBlock(addr); else if (lru_net) - blk = lru_net->findBlock(addr, asid); + blk = lru_net->findBlock(addr); if (!blk) return; @@ -422,15 +422,15 @@ Split::invalidateBlk(int asid, Addr addr) } void -Split::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) +Split::doCopy(Addr source, Addr dest, PacketList &writebacks) { - if (lru->probe(asid, source)) - lru->doCopy(source, dest, asid, writebacks); + if (lru->probe( source)) + lru->doCopy(source, dest, writebacks); else { if (lifo && lifo_net) - lifo_net->doCopy(source, dest, asid, writebacks); + lifo_net->doCopy(source, dest, writebacks); else if (lru_net) - lru_net->doCopy(source, dest, asid, writebacks); + lru_net->doCopy(source, dest, writebacks); } } diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh index 25180a02b..f0091e971 100644 --- a/src/mem/cache/tags/split.hh +++ b/src/mem/cache/tags/split.hh @@ -181,14 +181,14 @@ class Split : public BaseTags * @param addr The address to find. * @return True if the address is in the cache. */ - bool probe(int asid, Addr addr) const; + bool probe(Addr addr) const; /** * Invalidate the block containing the given address. * @param asid The address space ID. * @param addr The address to invalidate. */ - void invalidateBlk(int asid, Addr addr); + void invalidateBlk(Addr addr); /** * Finds the given address in the cache and update replacement data. @@ -198,7 +198,7 @@ class Split : public BaseTags * @param lat The access latency. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Addr addr, int asid, int &lat); + SplitBlk* findBlock(Addr addr, int &lat); /** * Finds the given address in the cache and update replacement data. @@ -215,7 +215,7 @@ class Split : public BaseTags * @param asid The address space ID. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Addr addr, int asid) const; + SplitBlk* findBlock(Addr addr) const; /** * Find a replacement block for the address provided. @@ -317,7 +317,7 @@ class Split : public BaseTags * @param asid The address space DI. * @param writebacks List for any generated writeback pktuests. */ - void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks); + void doCopy(Addr source, Addr dest, PacketList &writebacks); /** * No impl. diff --git a/src/mem/cache/tags/split_lifo.cc b/src/mem/cache/tags/split_lifo.cc index f6493fdd2..6fcbf3597 100644 --- a/src/mem/cache/tags/split_lifo.cc +++ b/src/mem/cache/tags/split_lifo.cc @@ -44,7 +44,7 @@ using namespace std; SplitBlk* -LIFOSet::findBlk(int asid, Addr tag) const +LIFOSet::findBlk(Addr tag) const { for (SplitBlk *blk = firstIn; blk != NULL; blk = blk->next) { if (blk->tag == tag && blk->isValid()) { @@ -216,21 +216,21 @@ SplitLIFO::regStats(const std::string &name) // probe cache for presence of given block. bool -SplitLIFO::probe(int asid, Addr addr) const +SplitLIFO::probe(Addr addr) const { Addr tag = extractTag(addr); unsigned myset = extractSet(addr); - SplitBlk* blk = sets[myset].findBlk(asid, tag); + SplitBlk* blk = sets[myset].findBlk(tag); return (blk != NULL); } SplitBlk* -SplitLIFO::findBlock(Addr addr, int asid, int &lat) +SplitLIFO::findBlock(Addr addr, int &lat) { Addr tag = extractTag(addr); unsigned set = extractSet(addr); - SplitBlk *blk = sets[set].findBlk(asid, tag); + SplitBlk *blk = sets[set].findBlk(tag); lat = hitLatency; @@ -258,11 +258,10 @@ SplitBlk* SplitLIFO::findBlock(Packet * &pkt, int &lat) { Addr addr = pkt->getAddr(); - int asid = pkt->req->getAsid(); Addr tag = extractTag(addr); unsigned set = extractSet(addr); - SplitBlk *blk = sets[set].findBlk(asid, tag); + SplitBlk *blk = sets[set].findBlk(tag); if (blk) { DPRINTF(Split, "Found LIFO blk %#x in set %d, with tag %#x\n", @@ -282,11 +281,11 @@ SplitLIFO::findBlock(Packet * &pkt, int &lat) } SplitBlk* -SplitLIFO::findBlock(Addr addr, int asid) const +SplitLIFO::findBlock(Addr addr) const { Addr tag = extractTag(addr); unsigned set = extractSet(addr); - SplitBlk *blk = sets[set].findBlk(asid, tag); + SplitBlk *blk = sets[set].findBlk(tag); return blk; } @@ -336,9 +335,9 @@ SplitLIFO::findReplacement(Packet * &pkt, PacketList &writebacks, } void -SplitLIFO::invalidateBlk(int asid, Addr addr) +SplitLIFO::invalidateBlk(Addr addr) { - SplitBlk *blk = findBlock(addr, asid); + SplitBlk *blk = findBlock(addr); if (blk) { blk->status = 0; blk->isTouched = false; @@ -348,15 +347,15 @@ SplitLIFO::invalidateBlk(int asid, Addr addr) } void -SplitLIFO::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) +SplitLIFO::doCopy(Addr source, Addr dest, PacketList &writebacks) { //Copy Unsuported for now #if 0 assert(source == blkAlign(source)); assert(dest == blkAlign(dest)); - SplitBlk *source_blk = findBlock(source, asid); + SplitBlk *source_blk = findBlock(source); assert(source_blk); - SplitBlk *dest_blk = findBlock(dest, asid); + SplitBlk *dest_blk = findBlock(dest); if (dest_blk == NULL) { // Need to do a replacement Packet * pkt = new Packet(); @@ -367,7 +366,6 @@ SplitLIFO::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) // Need to writeback data. pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag, dest_blk->set), - dest_blk->req->asid, dest_blk->xc, blkSize, (cache->doData())?dest_blk->data:0, @@ -375,7 +373,6 @@ SplitLIFO::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) writebacks.push_back(pkt); } dest_blk->tag = extractTag(dest); - dest_blk->req->asid = asid; /** * @todo Do we need to pass in the execution context, or can we * assume its the same? diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh index 52956b192..355a66162 100644 --- a/src/mem/cache/tags/split_lifo.hh +++ b/src/mem/cache/tags/split_lifo.hh @@ -73,7 +73,7 @@ class LIFOSet { * @param tag the Tag you are looking for * @return Pointer to the block, if found, NULL otherwise */ - SplitBlk* findBlk(int asid, Addr tag) const; + SplitBlk* findBlk(Addr tag) const; void moveToLastIn(SplitBlk *blk); void moveToFirstIn(SplitBlk *blk); @@ -181,14 +181,14 @@ public: * @param addr The address to find. * @return True if the address is in the cache. */ - bool probe(int asid, Addr addr) const; + bool probe( Addr addr) const; /** * Invalidate the block containing the given address. * @param asid The address space ID. * @param addr The address to invalidate. */ - void invalidateBlk(int asid, Addr addr); + void invalidateBlk(Addr addr); /** * Finds the given address in the cache and update replacement data. @@ -198,7 +198,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Addr addr, int asid, int &lat); + SplitBlk* findBlock(Addr addr, int &lat); /** * Finds the given address in the cache and update replacement data. @@ -215,7 +215,7 @@ public: * @param asid The address space ID. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Addr addr, int asid) const; + SplitBlk* findBlock(Addr addr) const; /** * Find a replacement block for the address provided. @@ -332,7 +332,7 @@ public: * @param asid The address space DI. * @param writebacks List for any generated writeback pktuests. */ - void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks); + void doCopy(Addr source, Addr dest, PacketList &writebacks); /** * No impl. diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc index 7fc742001..4381923bd 100644 --- a/src/mem/cache/tags/split_lru.cc +++ b/src/mem/cache/tags/split_lru.cc @@ -43,7 +43,7 @@ using namespace std; SplitBlk* -SplitCacheSet::findBlk(int asid, Addr tag) const +SplitCacheSet::findBlk(Addr tag) const { for (int i = 0; i < assoc; ++i) { if (blks[i]->tag == tag && blks[i]->isValid()) { @@ -135,7 +135,6 @@ SplitLRU::SplitLRU(int _numSets, int _blkSize, int _assoc, int _hit_latency, int // table; won't matter because the block is invalid blk->tag = j; blk->whenReady = 0; - blk->asid = -1; blk->isTouched = false; blk->size = blkSize; sets[i].blks[j]=blk; @@ -172,23 +171,23 @@ SplitLRU::regStats(const std::string &name) // probe cache for presence of given block. bool -SplitLRU::probe(int asid, Addr addr) const +SplitLRU::probe(Addr addr) const { // return(findBlock(Read, addr, asid) != 0); Addr tag = extractTag(addr); unsigned myset = extractSet(addr); - SplitBlk *blk = sets[myset].findBlk(asid, tag); + SplitBlk *blk = sets[myset].findBlk(tag); return (blk != NULL); // true if in cache } SplitBlk* -SplitLRU::findBlock(Addr addr, int asid, int &lat) +SplitLRU::findBlock(Addr addr, int &lat) { Addr tag = extractTag(addr); unsigned set = extractSet(addr); - SplitBlk *blk = sets[set].findBlk(asid, tag); + SplitBlk *blk = sets[set].findBlk(tag); lat = hitLatency; if (blk != NULL) { // move this block to head of the MRU list @@ -207,11 +206,10 @@ SplitBlk* SplitLRU::findBlock(Packet * &pkt, int &lat) { Addr addr = pkt->getAddr(); - int asid = pkt->req->getAsid(); Addr tag = extractTag(addr); unsigned set = extractSet(addr); - SplitBlk *blk = sets[set].findBlk(asid, tag); + SplitBlk *blk = sets[set].findBlk(tag); lat = hitLatency; if (blk != NULL) { // move this block to head of the MRU list @@ -227,11 +225,11 @@ SplitLRU::findBlock(Packet * &pkt, int &lat) } SplitBlk* -SplitLRU::findBlock(Addr addr, int asid) const +SplitLRU::findBlock(Addr addr) const { Addr tag = extractTag(addr); unsigned set = extractSet(addr); - SplitBlk *blk = sets[set].findBlk(asid, tag); + SplitBlk *blk = sets[set].findBlk(tag); return blk; } @@ -263,9 +261,9 @@ SplitLRU::findReplacement(Packet * &pkt, PacketList &writebacks, } void -SplitLRU::invalidateBlk(int asid, Addr addr) +SplitLRU::invalidateBlk(Addr addr) { - SplitBlk *blk = findBlock(addr, asid); + SplitBlk *blk = findBlock(addr); if (blk) { blk->status = 0; blk->isTouched = false; @@ -274,15 +272,15 @@ SplitLRU::invalidateBlk(int asid, Addr addr) } void -SplitLRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) +SplitLRU::doCopy(Addr source, Addr dest, PacketList &writebacks) { //Copy not supported for now #if 0 assert(source == blkAlign(source)); assert(dest == blkAlign(dest)); - SplitBlk *source_blk = findBlock(source, asid); + SplitBlk *source_blk = findBlock(source); assert(source_blk); - SplitBlk *dest_blk = findBlock(dest, asid); + SplitBlk *dest_blk = findBlock(dest); if (dest_blk == NULL) { // Need to do a replacement Packet * pkt = new Packet(); @@ -293,7 +291,6 @@ SplitLRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) // Need to writeback data. pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag, dest_blk->set), - dest_blk->req->asid, dest_blk->xc, blkSize, (cache->doData())?dest_blk->data:0, @@ -301,7 +298,6 @@ SplitLRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks) writebacks.push_back(pkt); } dest_blk->tag = extractTag(dest); - dest_blk->req->asid = asid; /** * @todo Do we need to pass in the execution context, or can we * assume its the same? diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh index 6d370c5dd..72aebac9c 100644 --- a/src/mem/cache/tags/split_lru.hh +++ b/src/mem/cache/tags/split_lru.hh @@ -65,7 +65,7 @@ class SplitCacheSet * @param tag The Tag to find. * @return Pointer to the block if found. */ - SplitBlk* findBlk(int asid, Addr tag) const; + SplitBlk* findBlk(Addr tag) const; /** * Move the given block to the head of the list. @@ -164,14 +164,14 @@ public: * @param addr The address to find. * @return True if the address is in the cache. */ - bool probe(int asid, Addr addr) const; + bool probe(Addr addr) const; /** * Invalidate the block containing the given address. * @param asid The address space ID. * @param addr The address to invalidate. */ - void invalidateBlk(int asid, Addr addr); + void invalidateBlk(Addr addr); /** * Finds the given address in the cache and update replacement data. @@ -181,7 +181,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Addr addr, int asid, int &lat); + SplitBlk* findBlock(Addr addr, int &lat); /** * Finds the given address in the cache and update replacement data. @@ -198,7 +198,7 @@ public: * @param asid The address space ID. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Addr addr, int asid) const; + SplitBlk* findBlock(Addr addr) const; /** * Find a replacement block for the address provided. @@ -315,7 +315,7 @@ public: * @param asid The address space DI. * @param writebacks List for any generated writeback pktuests. */ - void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks); + void doCopy(Addr source, Addr dest, PacketList &writebacks); /** * No impl. -- cgit v1.2.3